gem5/src/arch/arm/insts
Ali Saidi 53ab306acc ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17 19:20:20 -05:00
..
branch.hh ARM: Identify branches as conditional or unconditional and direct or indirect. 2011-03-17 19:20:20 -05:00
macromem.cc ARM: Fix subtle bug in LDM. 2011-03-17 19:20:20 -05:00
macromem.hh ARM: Fix RFE macrop. 2011-03-17 19:20:19 -05:00
mem.cc ARM: Make some of the trace code more compact 2010-06-02 12:58:18 -05:00
mem.hh ARM: Fix RFE macrop. 2011-03-17 19:20:19 -05:00
misc.cc ARM: Get rid of the binary dumping function in utility.hh. 2010-06-02 12:58:17 -05:00
misc.hh ARM: Make undefined instructions obey predication. 2010-06-02 12:58:16 -05:00
mult.hh ARM: Add base classes for multiply instructions. 2010-06-02 12:58:03 -05:00
pred_inst.cc ARM: Get rid of obsoleted predicated inst formats, etc. 2010-06-02 12:58:02 -05:00
pred_inst.hh ARM: The ARM decoder should not panic when decoding undefined holes is arch. 2011-01-18 16:30:05 -06:00
static_inst.cc ARM: Don't rely on undefined behavior to get arithmetic right shift. 2010-06-02 12:58:04 -05:00
static_inst.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
vfp.cc ARM: Implement all ARM SIMD instructions. 2010-08-25 19:10:42 -05:00
vfp.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00