2399 lines
277 KiB
Text
2399 lines
277 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.550461 # Number of seconds simulated
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sim_ticks 2550460850000 # Number of ticks simulated
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final_tick 2550460850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 71467 # Simulator instruction rate (inst/s)
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host_op_rate 91959 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3022122690 # Simulator tick rate (ticks/s)
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host_mem_usage 427404 # Number of bytes of host memory used
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host_seconds 843.93 # Real time elapsed on the host
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sim_insts 60313440 # Number of instructions simulated
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sim_ops 77607116 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 504512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 5067800 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 293824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4027288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 131006896 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 504512 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 293824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 798336 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3786560 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1521444 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 1494656 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6802660 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 7883 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 79220 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 4591 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 62932 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15293488 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59165 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 380361 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 373664 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813190 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47485743 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 197812 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1987013 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 115204 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1579043 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51365970 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 197812 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 115204 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 313016 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1484657 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 596537 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 586034 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2667228 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1484657 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47485743 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 197812 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 2583550 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 115204 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 2165077 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54033198 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15293488 # Number of read requests accepted
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system.physmem.writeReqs 813190 # Number of write requests accepted
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system.physmem.readBursts 15293488 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 813190 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 978237376 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 545856 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6910336 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 131006896 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6802660 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 8529 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 705216 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4690 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 955874 # Per bank write bursts
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system.physmem.perBankRdBursts::1 955460 # Per bank write bursts
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system.physmem.perBankRdBursts::2 954683 # Per bank write bursts
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system.physmem.perBankRdBursts::3 954757 # Per bank write bursts
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system.physmem.perBankRdBursts::4 955767 # Per bank write bursts
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system.physmem.perBankRdBursts::5 955952 # Per bank write bursts
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system.physmem.perBankRdBursts::6 954810 # Per bank write bursts
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system.physmem.perBankRdBursts::7 954709 # Per bank write bursts
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system.physmem.perBankRdBursts::8 956270 # Per bank write bursts
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system.physmem.perBankRdBursts::9 955934 # Per bank write bursts
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system.physmem.perBankRdBursts::10 954560 # Per bank write bursts
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system.physmem.perBankRdBursts::11 953973 # Per bank write bursts
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system.physmem.perBankRdBursts::12 956221 # Per bank write bursts
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system.physmem.perBankRdBursts::13 955978 # Per bank write bursts
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system.physmem.perBankRdBursts::14 955151 # Per bank write bursts
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system.physmem.perBankRdBursts::15 954860 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6693 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6460 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6602 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6635 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6566 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6824 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6825 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6757 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7131 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6880 # Per bank write bursts
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|
system.physmem.perBankWrBursts::10 6546 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6195 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7145 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6763 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7046 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6906 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2550459728500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 44 # Read request sizes (log2)
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system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 154628 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754025 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 59165 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1189211 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1129031 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1083368 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3689725 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2647408 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2642045 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2653706 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 51340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 57140 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 20388 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 20349 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 20322 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 20287 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 20234 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 20199 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 4924 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 5663 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 5202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4936 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4915 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4840 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4820 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 4777 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 4773 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 4768 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 4711 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 4718 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 4739 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 4690 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 4693 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 5053 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 129 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 86806 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 11348.833952 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 1015.155739 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 16835.722240 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-71 23589 27.17% 27.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-135 14167 16.32% 43.49% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::192-199 2667 3.07% 46.57% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-263 2091 2.41% 48.98% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::320-327 1355 1.56% 50.54% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-391 1138 1.31% 51.85% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::448-455 864 1.00% 52.84% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-519 1120 1.29% 54.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::576-583 549 0.63% 54.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-647 610 0.70% 55.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-711 512 0.59% 56.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-775 456 0.53% 56.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-839 243 0.28% 56.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-903 296 0.34% 57.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-967 156 0.18% 57.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1031 592 0.68% 58.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1095 118 0.14% 58.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1159 142 0.16% 58.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1223 67 0.08% 58.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1287 249 0.29% 58.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1351 52 0.06% 58.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1415 529 0.61% 59.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1543 292 0.34% 59.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1607 23 0.03% 59.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1671 99 0.11% 59.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1735 19 0.02% 59.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1799 187 0.22% 60.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1927 47 0.05% 60.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1991 18 0.02% 60.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2055 308 0.35% 60.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2119 8 0.01% 60.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2183 37 0.04% 60.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2247 15 0.02% 60.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2311 167 0.19% 60.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2567 29 0.03% 60.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2631 15 0.02% 60.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2695 19 0.02% 60.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2759 10 0.01% 61.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2823 208 0.24% 61.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2951 29 0.03% 61.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3079 407 0.47% 61.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3143 12 0.01% 61.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3207 20 0.02% 61.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3335 80 0.09% 61.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3463 13 0.01% 61.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3527 7 0.01% 61.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3591 84 0.10% 62.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3719 19 0.02% 62.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3847 152 0.18% 62.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4039 9 0.01% 62.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4103 349 0.40% 62.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4167 12 0.01% 62.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4231 10 0.01% 62.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4295 13 0.01% 62.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4359 21 0.02% 62.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4423 11 0.01% 62.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4615 184 0.21% 63.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4679 10 0.01% 63.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4807 12 0.01% 63.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4871 8 0.01% 63.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4999 12 0.01% 63.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5127 273 0.31% 63.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5383 208 0.24% 63.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5575 7 0.01% 63.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5639 73 0.08% 63.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5703 5 0.01% 63.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5767 17 0.02% 63.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5895 138 0.16% 63.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6023 13 0.01% 64.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6087 5 0.01% 64.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6151 459 0.53% 64.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6407 9 0.01% 64.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6663 12 0.01% 64.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6791 19 0.02% 64.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6855 4 0.00% 64.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6919 133 0.15% 64.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7047 4 0.00% 64.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7175 263 0.30% 65.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7431 14 0.02% 65.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7559 26 0.03% 65.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7687 188 0.22% 65.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7815 3 0.00% 65.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7943 68 0.08% 65.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8007 5 0.01% 65.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8135 2 0.00% 65.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8455 64 0.07% 66.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8711 184 0.21% 66.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8967 4 0.00% 66.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9223 261 0.30% 66.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9479 128 0.15% 66.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9735 3 0.00% 66.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9991 4 0.00% 66.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10247 451 0.52% 67.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10759 63 0.07% 67.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11015 194 0.22% 67.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11072-11079 1 0.00% 67.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11271 259 0.30% 68.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11783 167 0.19% 68.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12039 5 0.01% 68.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12295 322 0.37% 68.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12480-12487 1 0.00% 68.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12551 135 0.16% 68.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12807 67 0.08% 68.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12864-12871 1 0.00% 68.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13063 55 0.06% 69.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13319 384 0.44% 69.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13575 185 0.21% 69.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13760-13767 1 0.00% 69.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13831 6 0.01% 69.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14087 126 0.15% 69.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14343 259 0.30% 70.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14599 129 0.15% 70.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14855 129 0.15% 70.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15111 124 0.14% 70.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15367 385 0.44% 71.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15623 3 0.00% 71.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15879 129 0.15% 71.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16135 67 0.08% 71.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16391 642 0.74% 71.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16448-16455 1 0.00% 71.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16647 65 0.07% 72.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16903 128 0.15% 72.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17408-17415 384 0.44% 72.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17600-17607 1 0.00% 72.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17671 123 0.14% 72.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17927 129 0.15% 72.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18183 129 0.15% 73.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18368-18375 1 0.00% 73.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18439 261 0.30% 73.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18695 126 0.15% 73.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18944-18951 6 0.01% 73.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19207 183 0.21% 73.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19719 55 0.06% 74.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-19975 67 0.08% 74.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20231 132 0.15% 74.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20487 322 0.37% 74.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20743 6 0.01% 74.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-20999 169 0.19% 75.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21248-21255 3 0.00% 75.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21511 256 0.29% 75.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22023 63 0.07% 75.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22279 64 0.07% 75.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22535 449 0.52% 76.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22784-22791 5 0.01% 76.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23047 3 0.00% 76.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23296-23303 129 0.15% 76.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23559 259 0.30% 76.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23815 4 0.00% 76.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23936-23943 1 0.00% 76.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24000-24007 1 0.00% 76.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24071 184 0.21% 76.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24583 497 0.57% 77.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24832-24839 65 0.07% 77.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25095 186 0.21% 77.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25351 4 0.00% 77.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25607 259 0.30% 78.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25856-25863 130 0.15% 78.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26119 2 0.00% 78.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26375 6 0.01% 78.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26631 449 0.52% 78.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26887 64 0.07% 78.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27136-27143 61 0.07% 79.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27399 194 0.22% 79.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27655 258 0.30% 79.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28160-28167 167 0.19% 79.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28423 5 0.01% 79.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28679 321 0.37% 80.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29191 66 0.08% 80.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29447 54 0.06% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29703 384 0.44% 80.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-29959 186 0.21% 81.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30215 7 0.01% 81.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30471 127 0.15% 81.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30727 260 0.30% 81.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30976-30983 130 0.15% 81.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31239 128 0.15% 81.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31360-31367 1 0.00% 81.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31495 123 0.14% 81.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32000-32007 3 0.00% 82.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32519 65 0.07% 82.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33287 128 0.15% 83.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33536-33543 3 0.00% 83.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34048-34055 123 0.14% 84.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34311 128 0.15% 84.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34560-34567 130 0.15% 84.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34823 260 0.30% 84.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35079 126 0.15% 84.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35328-35335 8 0.01% 84.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35520-35527 1 0.00% 84.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35591 185 0.21% 85.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35847 384 0.44% 85.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36096-36103 55 0.06% 85.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36352-36359 67 0.08% 85.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36608-36615 130 0.15% 85.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36871 321 0.37% 86.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37120-37127 5 0.01% 86.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37376-37383 165 0.19% 86.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37895 258 0.30% 86.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38151 194 0.22% 86.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38407 60 0.07% 87.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38656-38663 64 0.07% 87.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38912-38919 449 0.52% 87.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39168-39175 5 0.01% 87.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39431 3 0.00% 87.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39680-39687 128 0.15% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40192-40199 4 0.00% 88.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40448-40455 186 0.21% 88.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-40967 498 0.57% 88.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41472-41479 183 0.21% 89.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41664-41671 1 0.00% 89.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41728-41735 4 0.00% 89.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-41991 258 0.30% 89.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42240-42247 128 0.15% 89.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42752-42759 4 0.00% 89.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43015 450 0.52% 90.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43271 65 0.07% 90.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43520-43527 59 0.07% 90.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43776-43783 195 0.22% 90.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44039 257 0.30% 90.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44224-44231 2 0.00% 90.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44352-44359 2 0.00% 90.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44551 168 0.19% 91.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44672-44679 1 0.00% 91.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44800-44807 6 0.01% 91.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44928-44935 2 0.00% 91.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45063 327 0.38% 91.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45568-45575 67 0.08% 91.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45831 55 0.06% 91.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46080-46087 386 0.44% 92.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46336-46343 185 0.21% 92.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46592-46599 6 0.01% 92.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46848-46855 126 0.15% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47111 260 0.30% 92.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47360-47367 129 0.15% 93.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47623 130 0.15% 93.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47872-47879 122 0.14% 93.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48135 386 0.44% 93.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48640-48647 129 0.15% 93.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48896-48903 65 0.07% 93.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48960-48967 2 0.00% 93.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49159 5210 6.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51008-51015 2 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51200-51207 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 86806 # Bytes accessed per row activation
|
|
system.physmem.totQLat 369546937250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 463545387250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 76424795000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 17573655000 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 24177.16 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 1149.74 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30326.90 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 383.55 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 15213019 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 93108 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 86.23 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 158347.97 # Average gap between requests
|
|
system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 54973413 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16346095 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16346098 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 59165 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4689 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4690 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 131440 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131440 # Transaction distribution
|
|
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
|
|
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
|
|
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885939 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4272691 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 34550323 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699028 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 19097009 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 140207537 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 140207537 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1487746500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 17566438500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4736460824 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 34185683234 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.l2c.tags.replacements 64398 # number of replacements
|
|
system.l2c.tags.tagsinuse 51440.737713 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1904463 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 129791 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 14.673306 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2513095359500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 36974.659237 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.382027 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4864.361052 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3325.264959 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.733963 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.979227 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 3333.561172 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 2910.795705 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.564189 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.074224 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.050740 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.050866 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.044415 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.784923 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65370 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6833 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55085 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.997467 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 18926387 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 18926387 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 32717 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 6688 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 507057 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 188596 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 30977 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 7027 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 463887 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 198617 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1435566 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 607936 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 607936 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 60659 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 52244 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 112903 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 32717 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 6688 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 507057 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 249255 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 30977 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 7027 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 463887 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 250861 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1548469 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 32717 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 6688 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 507057 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 249255 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 30977 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 7027 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 463887 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 250861 # number of overall hits
|
|
system.l2c.overall_hits::total 1548469 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7772 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6310 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 4598 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 4426 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 23152 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1623 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1291 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2914 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 73806 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 59409 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 133215 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7772 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 80116 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 4598 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 63835 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 156367 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7772 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 80116 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 4598 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 63835 # number of overall misses
|
|
system.l2c.overall_misses::total 156367 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2411500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 562480250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 472355249 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1382500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 339266250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 344164000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1722292749 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 162493 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 280988 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 443481 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5508293110 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4400568365 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 9908861475 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 2411500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 562480250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 5980648359 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 1382500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 339266250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 4744732365 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 11631154224 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 2411500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 562480250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 5980648359 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 1382500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 339266250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 4744732365 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 11631154224 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 32746 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 6690 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 514829 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 194906 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 30991 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 7028 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 468485 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 203043 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1458718 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 607936 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 607936 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1642 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1308 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 134465 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 111653 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 246118 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 32746 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 6690 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 514829 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 329371 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 30991 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 7028 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 468485 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 314696 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1704836 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 32746 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 6690 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 514829 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 329371 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 30991 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 7028 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 468485 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 314696 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1704836 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000299 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015096 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.032375 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000142 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009815 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.021798 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.015871 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988429 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987003 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.987797 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.250000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.125000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.548886 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.532086 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.541265 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000299 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015096 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.243239 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000142 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.009815 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.202847 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.091720 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000886 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000299 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015096 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.243239 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000452 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000142 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.009815 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.202847 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.091720 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72372.651827 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74858.201109 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 98750 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73785.613310 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77759.602350 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 74390.668150 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 100.118916 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 217.651433 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 152.189774 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74632.050375 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74072.419415 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 74382.475510 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 72372.651827 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 74649.862187 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98750 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 73785.613310 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 74328.070259 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 74383.688528 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83155.172414 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 72372.651827 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 74649.862187 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98750 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 73785.613310 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 74328.070259 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 74383.688528 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 59165 # number of writebacks
|
|
system.l2c.writebacks::total 59165 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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system.l2c.ReadReq_mshr_misses::total 23070 # number of ReadReq MSHR misses
|
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|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1291 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 2914 # number of UpgradeReq MSHR misses
|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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system.l2c.ReadReq_mshr_miss_latency::total 1427924749 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12916289 # number of UpgradeReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::total 29147912 # number of UpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles
|
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system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
|
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6162749 # number of ReadReq MSHR uncacheable cycles
|
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|
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83128929250 # number of ReadReq MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::total 166943376499 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8942076738 # number of WriteReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8427643000 # number of WriteReq MSHR uncacheable cycles
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|
system.l2c.WriteReq_mshr_uncacheable_latency::total 17369719738 # number of WriteReq MSHR uncacheable cycles
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system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6162749 # number of overall MSHR uncacheable cycles
|
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system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92750361238 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91556572250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 184313096237 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for ReadReq accesses
|
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system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032149 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses
|
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system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021680 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.015815 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988429 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987003 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.987797 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.125000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548886 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.532086 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.243106 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.202770 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.091672 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000886 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.243106 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.202770 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.091672 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62413.381583 # average ReadReq mshr miss latency
|
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65404.248069 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 61895.307716 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.871418 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.715168 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62155.866596 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61603.993250 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61909.751342 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency
|
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system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
|
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system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency
|
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system.l2c.demand_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency
|
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
|
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system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency
|
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system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency
|
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system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 58420424 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 2676760 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2676762 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 607936 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 246118 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 246118 # Transaction distribution
|
|
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968062 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796874 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37580 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149966 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7952482 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62939648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85542385 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254948 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size::total 148791853 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 148791853 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 207152 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4962468234 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4433875230 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4484319469 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 23911393 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 86679578 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 48422959 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 123500861 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41495326766 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
system.cpu0.branchPred.lookups 7528776 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 6012881 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 377531 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 4829761 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 3930404 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 81.378851 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 724348 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 39225 # Number of incorrect RAS predictions.
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 25731693 # DTB read hits
|
|
system.cpu0.dtb.read_misses 40178 # DTB read misses
|
|
system.cpu0.dtb.write_hits 6168711 # DTB write hits
|
|
system.cpu0.dtb.write_misses 10337 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5677 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 1369 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 25771871 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 6179048 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 31900404 # DTB hits
|
|
system.cpu0.dtb.misses 50515 # DTB misses
|
|
system.cpu0.dtb.accesses 31950919 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 5899860 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 7207 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2688 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1562 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 5907067 # ITB inst accesses
|
|
system.cpu0.itb.hits 5899860 # DTB hits
|
|
system.cpu0.itb.misses 7207 # DTB misses
|
|
system.cpu0.itb.accesses 5907067 # DTB accesses
|
|
system.cpu0.numCycles 242297109 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 15555542 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 45617593 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 7528776 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 4654752 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 10311247 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2439507 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 83051 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 50330649 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 1691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingDrainCycles 2002 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu0.fetch.PendingTrapStallCycles 48587 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 1491133 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 722 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 5897866 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 368478 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 3041 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 79507031 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.722707 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.070799 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 69202528 87.04% 87.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 678265 0.85% 87.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 875305 1.10% 88.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1177307 1.48% 90.47% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 1118218 1.41% 91.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 557082 0.70% 92.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 1282023 1.61% 94.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 381348 0.48% 94.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 4234955 5.33% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 79507031 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.031072 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.188271 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 16656471 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 51363244 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 9231902 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 659908 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1593273 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 1005882 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 91811 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 54700033 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 305616 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1593273 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 17552192 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 20324540 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 27741870 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 8932000 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 3360998 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 52127379 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 375 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 510306 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 2174045 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 221 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 53799249 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 241745694 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 220537236 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 5112 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 39397526 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 14401722 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 594296 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 542687 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 6992906 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 10039494 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6994522 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1049493 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1384753 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 48432856 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1029992 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 62172633 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 89012 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 9963233 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 24631985 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 276940 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 79507031 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.781977 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.500620 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 56951176 71.63% 71.63% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 7375765 9.28% 80.91% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3517120 4.42% 85.33% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2922983 3.68% 89.01% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 6158188 7.75% 96.75% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1492282 1.88% 98.63% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 793715 1.00% 99.63% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 229189 0.29% 99.92% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 66613 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 79507031 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 30271 0.68% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 4195541 94.33% 95.01% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 221720 4.99% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 15963 0.03% 0.03% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 29223949 47.00% 47.03% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 47621 0.08% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 1246 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 26409062 42.48% 89.59% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 6474770 10.41% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 62172633 # Type of FU issued
|
|
system.cpu0.iq.rate 0.256597 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 4447534 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.071535 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 208427694 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 59435167 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 43384407 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 11467 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 6219 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5237 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 66598153 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 6051 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 313701 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2134408 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 15882 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 849708 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 17067409 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 348218 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1593273 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 15683016 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 239861 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 49569735 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 107283 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 10039494 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6994522 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 730989 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 55378 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 15882 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 184147 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 145491 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 329638 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 61106002 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 26080146 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1066631 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 106887 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 32497006 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 5987699 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 6416860 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.252195 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 60612995 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 43389644 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 23417175 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 43060015 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.179076 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.543826 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 9791777 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 753052 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 287149 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 77913758 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.504003 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.469415 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 63454715 81.44% 81.44% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 7423327 9.53% 90.97% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1988141 2.55% 93.52% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 1098394 1.41% 94.93% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 861624 1.11% 96.04% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 581195 0.75% 96.78% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 738806 0.95% 97.73% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 351756 0.45% 98.18% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1415800 1.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 77913758 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 30063645 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 39268790 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 14049900 # Number of memory references committed
|
|
system.cpu0.commit.loads 7905086 # Number of loads committed
|
|
system.cpu0.commit.membars 209983 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 5182251 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 5199 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 34974968 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 508855 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 1415800 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 124579792 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 99757537 # The number of ROB writes
|
|
system.cpu0.timesIdled 906870 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 162790078 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 2250741366 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 29991762 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 39196907 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 29991762 # Number of Instructions Simulated
|
|
system.cpu0.cpi 8.078789 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 8.078789 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.123781 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.123781 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 277582728 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 44079568 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 44948 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 42562 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 138472263 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 583698 # number of misc regfile writes
|
|
system.cpu0.icache.tags.replacements 983976 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.534971 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 10503842 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 984488 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 10.669345 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 7011386250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.535325 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.999646 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620186 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378906 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999092 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 12554064 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 12554064 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5339906 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 5163936 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 10503842 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5339906 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 5163936 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 10503842 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5339906 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 5163936 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 10503842 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 557837 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 507875 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1065712 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 557837 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 507875 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1065712 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 557837 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 507875 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1065712 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7709624467 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6833167274 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 14542791741 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 7709624467 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 6833167274 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 14542791741 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 7709624467 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 6833167274 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 14542791741 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5897743 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5671811 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 11569554 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 5897743 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 5671811 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 11569554 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 5897743 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 5671811 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 11569554 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094585 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089544 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094585 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089544 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094585 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089544 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.568494 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.427318 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13646.080499 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.568494 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13454.427318 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13646.080499 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.568494 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13454.427318 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13646.080499 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 7635 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 377 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.251989 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42413 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38788 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 81201 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 42413 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu1.inst 38788 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 81201 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 42413 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu1.inst 38788 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 81201 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 515424 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469087 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 984511 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 515424 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 469087 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 984511 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 515424 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 469087 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 984511 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6265245391 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5558732594 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11823977985 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6265245391 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5558732594 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11823977985 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6265245391 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5558732594 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11823977985 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8638250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8638250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8638250 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8638250 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085095 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.085095 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.085095 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12010.000889 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 643555 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.993287 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 21527522 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 644067 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 33.424352 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 43200250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.501132 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.492155 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500979 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499008 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 101636995 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 101636995 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 7028225 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 6743962 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13772187 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3755786 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3505627 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 7261413 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117401 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125757 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 243158 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120052 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127593 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247645 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10784011 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 10249589 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 21033600 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10784011 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 10249589 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 21033600 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 339066 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 409132 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 748198 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1643950 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 1318126 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 2962076 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7538 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6009 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13547 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1983016 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 1727258 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3710274 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1983016 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 1727258 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3710274 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5448026578 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5983783737 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 11431810315 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84542718469 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64782602600 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 149325321069 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 108200746 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 80635496 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 188836242 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 64501 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 116501 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 89990745047 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 70766386337 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 160757131384 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 89990745047 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 70766386337 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 160757131384 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7367291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7153094 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 14520385 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5399736 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4823753 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10223489 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124939 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131766 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 256705 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120056 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127597 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247653 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12767027 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 11976847 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 24743874 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12767027 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 11976847 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 24743874 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046023 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057197 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.051527 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.304450 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.273257 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.289732 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060333 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045604 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052773 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000033 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000031 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.155323 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.144216 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.149947 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155323 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.144216 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.149947 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16067.746628 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14625.557857 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.124396 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51426.575303 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49147.503805 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50412.386809 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14354.039002 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13419.120652 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13939.340223 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16125.250000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14562.625000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45380.745817 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40970.362469 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 43327.563243 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45380.745817 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40970.362469 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 43327.563243 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 36899 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 27773 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 3449 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 287 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.698463 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 96.770035 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 607936 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 607936 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 150881 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211427 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 362308 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1507904 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1205220 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 2713124 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 756 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 616 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1372 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658785 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1416647 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 3075432 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658785 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1416647 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 3075432 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188185 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 197705 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 385890 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136046 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112906 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 248952 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6782 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5393 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 324231 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 310611 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 634842 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 324231 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 310611 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 634842 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2625949736 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2626651360 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5252601096 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6397854586 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5145719244 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11543573830 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 85584754 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62638004 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148222758 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56499 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 100499 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9023804322 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7772370604 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 16796174926 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9023804322 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7772370604 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 16796174926 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527403500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90803265751 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330669251 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13693631022 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13075286221 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26768917243 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105221034522 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103878551972 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209099586494 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025543 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027639 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026576 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025195 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023406 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054282 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040929 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047428 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000033 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025657 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025657 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13954.086330 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13285.710326 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13611.653829 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47027.142187 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45575.250598 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46368.672796 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12619.397523 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11614.686445 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12174.353840 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14124.750000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12562.375000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 7298811 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 5882879 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 344498 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 4442454 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 3749763 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 84.407469 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 676814 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 34330 # Number of incorrect RAS predictions.
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 25485052 # DTB read hits
|
|
system.cpu1.dtb.read_misses 36401 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5542090 # DTB write hits
|
|
system.cpu1.dtb.write_misses 8345 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 5452 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 1278 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 25521453 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5550435 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 31027142 # DTB hits
|
|
system.cpu1.dtb.misses 44746 # DTB misses
|
|
system.cpu1.dtb.accesses 31071888 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 5673835 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 6882 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2658 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 1447 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 5680717 # ITB inst accesses
|
|
system.cpu1.itb.hits 5673835 # DTB hits
|
|
system.cpu1.itb.misses 6882 # DTB misses
|
|
system.cpu1.itb.accesses 5680717 # DTB accesses
|
|
system.cpu1.numCycles 236975623 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 14429172 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 45037398 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 7298811 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 4426577 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 9907364 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 2282600 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 82705 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 49394158 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 1073 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu1.fetch.PendingTrapStallCycles 44118 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 1230431 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 5671812 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 352198 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 3013 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 76664255 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.724522 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.076690 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 66765211 87.09% 87.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 630389 0.82% 87.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 841220 1.10% 89.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 1125492 1.47% 90.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 998152 1.30% 91.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 547084 0.71% 92.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1279264 1.67% 94.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 367549 0.48% 94.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 4109894 5.36% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 76664255 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.030800 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.190051 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 15533095 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 50132740 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 8857878 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 647971 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1490380 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 961231 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 85259 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 52933701 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 285543 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1490380 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 16375879 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 19322833 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 27622785 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 8617835 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 3232383 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 50467558 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 173 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 596710 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 2000524 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 626 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 52901652 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 233465152 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 213426027 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 5240 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 39335356 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 13566296 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 577962 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 535418 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 6495060 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 9746539 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 6334911 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 894923 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1137674 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 46958643 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 959615 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 60863950 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 85447 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 9232783 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 23424311 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 229955 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 76664255 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.793903 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.504568 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 54480181 71.06% 71.06% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 7304682 9.53% 80.59% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 3460273 4.51% 85.11% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 2866704 3.74% 88.84% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 6125054 7.99% 96.83% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1372858 1.79% 98.62% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 769548 1.00% 99.63% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 222824 0.29% 99.92% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 62131 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 76664255 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 29010 0.66% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 4179738 94.96% 95.62% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 192807 4.38% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 12555 0.02% 0.02% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 28808011 47.33% 47.35% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 45980 0.08% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 26140692 42.95% 90.38% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 5855817 9.62% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 60863950 # Type of FU issued
|
|
system.cpu1.iq.rate 0.256836 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 4401559 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.072318 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 202912608 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 57159577 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 42178137 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 11121 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 6181 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5062 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 65247126 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 5828 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 310626 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 1995012 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 2960 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 15279 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 746422 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 17045290 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 332871 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1490380 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 14881654 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 224199 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 48035025 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 95776 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 9746539 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 6334911 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 685011 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 49572 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 5137 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 15279 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 166909 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 134382 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 301291 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 59839107 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 25823960 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1024843 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 116767 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 31629946 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 5849908 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 5805986 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.252512 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 59372558 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 42183199 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 23508004 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 42759548 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.178006 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.549772 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 9155270 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 729660 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 260542 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 75173875 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.511996 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.483358 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 60919870 81.04% 81.04% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 7446257 9.91% 90.94% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 1922213 2.56% 93.50% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1068282 1.42% 94.92% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 820469 1.09% 96.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 498258 0.66% 96.68% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 699309 0.93% 97.61% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 369578 0.49% 98.10% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1429639 1.90% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 75173875 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 30400176 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 38488707 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 13340016 # Number of memory references committed
|
|
system.cpu1.commit.loads 7751527 # Number of loads committed
|
|
system.cpu1.commit.membars 193715 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 5124652 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 5013 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 34222153 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 482564 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 1429639 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 120517356 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 96821590 # The number of ROB writes
|
|
system.cpu1.timesIdled 866519 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 160311368 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 2319089759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 30321678 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 38410209 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 30321678 # Number of Instructions Simulated
|
|
system.cpu1.cpi 7.815386 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 7.815386 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.127953 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.127953 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 271574951 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 43566618 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 45165 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 42266 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 132802747 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 590318 # number of misc regfile writes
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1518508564766 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1518508564766 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 83065 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|