698767e538
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
224 lines
6.7 KiB
C++
224 lines
6.7 KiB
C++
/*
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* Copyright (c) 2012-2013,2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#ifndef __CPU_SIMPLE_ATOMIC_HH__
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#define __CPU_SIMPLE_ATOMIC_HH__
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#include "cpu/simple/base.hh"
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#include "cpu/simple/exec_context.hh"
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#include "mem/request.hh"
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#include "params/AtomicSimpleCPU.hh"
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#include "sim/probe/probe.hh"
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class AtomicSimpleCPU : public BaseSimpleCPU
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{
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public:
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AtomicSimpleCPU(AtomicSimpleCPUParams *params);
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virtual ~AtomicSimpleCPU();
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void init() override;
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private:
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struct TickEvent : public Event
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{
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AtomicSimpleCPU *cpu;
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TickEvent(AtomicSimpleCPU *c);
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void process();
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const char *description() const;
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};
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TickEvent tickEvent;
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const int width;
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bool locked;
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const bool simulate_data_stalls;
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const bool simulate_inst_stalls;
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// main simulation loop (one cycle)
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void tick();
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/**
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* Check if a system is in a drained state.
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*
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* We need to drain if:
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* <ul>
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* <li>We are in the middle of a microcode sequence as some CPUs
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* (e.g., HW accelerated CPUs) can't be started in the middle
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* of a gem5 microcode sequence.
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*
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* <li>The CPU is in a LLSC region. This shouldn't normally happen
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* as these are executed atomically within a single tick()
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* call. The only way this can happen at the moment is if
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* there is an event in the PC event queue that affects the
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* CPU state while it is in an LLSC region.
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*
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* <li>Stay at PC is true.
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* </ul>
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*/
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bool isDrained() {
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SimpleExecContext &t_info = *threadInfo[curThread];
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return t_info.thread->microPC() == 0 &&
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!locked &&
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!t_info.stayAtPC;
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}
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/**
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* Try to complete a drain request.
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*
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* @returns true if the CPU is drained, false otherwise.
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*/
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bool tryCompleteDrain();
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/**
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* An AtomicCPUPort overrides the default behaviour of the
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* recvAtomicSnoop and ignores the packet instead of panicking. It
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* also provides an implementation for the purely virtual timing
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* functions and panics on either of these.
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*/
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class AtomicCPUPort : public MasterPort
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{
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public:
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AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
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: MasterPort(_name, _cpu)
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{ }
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protected:
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bool recvTimingResp(PacketPtr pkt)
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{
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panic("Atomic CPU doesn't expect recvTimingResp!\n");
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return true;
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}
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void recvReqRetry()
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{
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panic("Atomic CPU doesn't expect recvRetry!\n");
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}
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};
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class AtomicCPUDPort : public AtomicCPUPort
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{
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public:
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AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
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: AtomicCPUPort(_name, _cpu), cpu(_cpu)
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{
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cacheBlockMask = ~(cpu->cacheLineSize() - 1);
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}
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bool isSnooping() const { return true; }
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Addr cacheBlockMask;
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protected:
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BaseSimpleCPU *cpu;
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virtual Tick recvAtomicSnoop(PacketPtr pkt);
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virtual void recvFunctionalSnoop(PacketPtr pkt);
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};
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AtomicCPUPort icachePort;
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AtomicCPUDPort dcachePort;
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bool fastmem;
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Request ifetch_req;
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Request data_read_req;
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Request data_write_req;
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bool dcache_access;
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Tick dcache_latency;
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/** Probe Points. */
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ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
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protected:
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/** Return a reference to the data port. */
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MasterPort &getDataPort() override { return dcachePort; }
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/** Return a reference to the instruction port. */
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MasterPort &getInstPort() override { return icachePort; }
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/** Perform snoop for other cpu-local thread contexts. */
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void threadSnoop(PacketPtr pkt, ThreadID sender);
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public:
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DrainState drain() override;
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void drainResume() override;
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void switchOut() override;
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void takeOverFrom(BaseCPU *oldCPU) override;
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void verifyMemoryMode() const override;
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void activateContext(ThreadID thread_num) override;
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void suspendContext(ThreadID thread_num) override;
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Fault readMem(Addr addr, uint8_t *data, unsigned size,
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Request::Flags flags) override;
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Fault initiateMemRead(Addr addr, unsigned size,
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Request::Flags flags) override;
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Fault writeMem(uint8_t *data, unsigned size,
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Addr addr, Request::Flags flags, uint64_t *res) override;
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void regProbePoints() override;
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/**
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* Print state of address in memory system via PrintReq (for
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* debugging).
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*/
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void printAddr(Addr a);
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};
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#endif // __CPU_SIMPLE_ATOMIC_HH__
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