770 lines
14 KiB
INI
770 lines
14 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
eventq_index=0
|
|
full_system=false
|
|
sim_quantum=0
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
|
|
|
|
[system]
|
|
type=System
|
|
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|
boot_osflags=a
|
|
cache_line_size=64
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
init_param=0
|
|
kernel=
|
|
load_addr_mask=1099511627775
|
|
load_offset=0
|
|
mem_mode=timing
|
|
mem_ranges=
|
|
memories=system.physmem
|
|
num_work_ids=16
|
|
readfile=
|
|
symbolfile=
|
|
work_begin_ckpt_count=0
|
|
work_begin_cpu_id_exit=-1
|
|
work_begin_exit_count=0
|
|
work_cpus_ckpt_count=0
|
|
work_end_ckpt_count=0
|
|
work_end_exit_count=0
|
|
work_item_id=-1
|
|
system_port=system.membus.slave[0]
|
|
|
|
[system.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=1000
|
|
eventq_index=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.cpu]
|
|
type=DerivO3CPU
|
|
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
|
LFSTSize=1024
|
|
LQEntries=32
|
|
LSQCheckLoads=true
|
|
LSQDepCheckShift=4
|
|
SQEntries=32
|
|
SSITSize=1024
|
|
activity=0
|
|
backComSize=5
|
|
branchPred=system.cpu.branchPred
|
|
cachePorts=200
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
commitToDecodeDelay=1
|
|
commitToFetchDelay=1
|
|
commitToIEWDelay=1
|
|
commitToRenameDelay=1
|
|
commitWidth=8
|
|
cpu_id=0
|
|
decodeToFetchDelay=1
|
|
decodeToRenameDelay=1
|
|
decodeWidth=8
|
|
dispatchWidth=8
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dstage2_mmu=system.cpu.dstage2_mmu
|
|
dtb=system.cpu.dtb
|
|
eventq_index=0
|
|
fetchBufferSize=64
|
|
fetchToDecodeDelay=1
|
|
fetchTrapLatency=1
|
|
fetchWidth=8
|
|
forwardComSize=5
|
|
fuPool=system.cpu.fuPool
|
|
function_trace=false
|
|
function_trace_start=0
|
|
iewToCommitDelay=1
|
|
iewToDecodeDelay=1
|
|
iewToFetchDelay=1
|
|
iewToRenameDelay=1
|
|
interrupts=system.cpu.interrupts
|
|
isa=system.cpu.isa
|
|
issueToExecuteDelay=1
|
|
issueWidth=8
|
|
istage2_mmu=system.cpu.istage2_mmu
|
|
itb=system.cpu.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
needsTSO=false
|
|
numIQEntries=64
|
|
numPhysCCRegs=0
|
|
numPhysFloatRegs=256
|
|
numPhysIntRegs=256
|
|
numROBEntries=192
|
|
numRobs=1
|
|
numThreads=1
|
|
profile=0
|
|
progress_interval=0
|
|
renameToDecodeDelay=1
|
|
renameToFetchDelay=1
|
|
renameToIEWDelay=2
|
|
renameToROBDelay=1
|
|
renameWidth=8
|
|
simpoint_start_insts=
|
|
smtCommitPolicy=RoundRobin
|
|
smtFetchPolicy=SingleThread
|
|
smtIQPolicy=Partitioned
|
|
smtIQThreshold=100
|
|
smtLSQPolicy=Partitioned
|
|
smtLSQThreshold=100
|
|
smtNumFetchingThreads=1
|
|
smtROBPolicy=Partitioned
|
|
smtROBThreshold=100
|
|
squashWidth=8
|
|
store_set_clear_period=250000
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu.tracer
|
|
trapLatency=13
|
|
wbDepth=1
|
|
wbWidth=8
|
|
workload=system.cpu.workload
|
|
dcache_port=system.cpu.dcache.cpu_side
|
|
icache_port=system.cpu.icache.cpu_side
|
|
|
|
[system.cpu.branchPred]
|
|
type=BranchPredictor
|
|
BTBEntries=4096
|
|
BTBTagSize=16
|
|
RASSize=16
|
|
choiceCtrBits=2
|
|
choicePredictorSize=8192
|
|
eventq_index=0
|
|
globalCtrBits=2
|
|
globalPredictorSize=8192
|
|
instShiftAmt=2
|
|
localCtrBits=2
|
|
localHistoryTableSize=2048
|
|
localPredictorSize=2048
|
|
numThreads=1
|
|
predType=tournament
|
|
|
|
[system.cpu.dcache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=2
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=262144
|
|
system=system
|
|
tags=system.cpu.dcache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.dcache_port
|
|
mem_side=system.cpu.toL2Bus.slave[1]
|
|
|
|
[system.cpu.dcache.tags]
|
|
type=LRU
|
|
assoc=2
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=2
|
|
sequential_access=false
|
|
size=262144
|
|
|
|
[system.cpu.dstage2_mmu]
|
|
type=ArmStage2MMU
|
|
children=stage2_tlb
|
|
eventq_index=0
|
|
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
|
tlb=system.cpu.dtb
|
|
|
|
[system.cpu.dstage2_mmu.stage2_tlb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=true
|
|
size=32
|
|
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|
|
|
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=true
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[5]
|
|
|
|
[system.cpu.dtb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=false
|
|
size=64
|
|
walker=system.cpu.dtb.walker
|
|
|
|
[system.cpu.dtb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=false
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[3]
|
|
|
|
[system.cpu.fuPool]
|
|
type=FUPool
|
|
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
|
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
|
eventq_index=0
|
|
|
|
[system.cpu.fuPool.FUList0]
|
|
type=FUDesc
|
|
children=opList
|
|
count=6
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList0.opList
|
|
|
|
[system.cpu.fuPool.FUList0.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=IntAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList1]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=2
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
|
|
|
[system.cpu.fuPool.FUList1.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=IntMult
|
|
opLat=3
|
|
|
|
[system.cpu.fuPool.FUList1.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=19
|
|
opClass=IntDiv
|
|
opLat=20
|
|
|
|
[system.cpu.fuPool.FUList2]
|
|
type=FUDesc
|
|
children=opList0 opList1 opList2
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
|
|
|
[system.cpu.fuPool.FUList2.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatAdd
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList2.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatCmp
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList2.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatCvt
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList3]
|
|
type=FUDesc
|
|
children=opList0 opList1 opList2
|
|
count=2
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
|
|
|
[system.cpu.fuPool.FUList3.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatMult
|
|
opLat=4
|
|
|
|
[system.cpu.fuPool.FUList3.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=12
|
|
opClass=FloatDiv
|
|
opLat=12
|
|
|
|
[system.cpu.fuPool.FUList3.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=24
|
|
opClass=FloatSqrt
|
|
opLat=24
|
|
|
|
[system.cpu.fuPool.FUList4]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList4.opList
|
|
|
|
[system.cpu.fuPool.FUList4.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5]
|
|
type=FUDesc
|
|
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
|
|
|
[system.cpu.fuPool.FUList5.opList00]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList01]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAddAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList02]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList03]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList04]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList05]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList06]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList07]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList08]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShift
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList09]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShiftAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList10]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList11]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList12]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList13]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList14]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList15]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatDiv
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList16]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList17]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList18]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList19]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList6]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList6.opList
|
|
|
|
[system.cpu.fuPool.FUList6.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
|
|
|
[system.cpu.fuPool.FUList7.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList8]
|
|
type=FUDesc
|
|
children=opList
|
|
count=1
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList8.opList
|
|
|
|
[system.cpu.fuPool.FUList8.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=3
|
|
opClass=IprAccess
|
|
opLat=3
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=2
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=131072
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=2
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=2
|
|
sequential_access=false
|
|
size=131072
|
|
|
|
[system.cpu.interrupts]
|
|
type=ArmInterrupts
|
|
eventq_index=0
|
|
|
|
[system.cpu.isa]
|
|
type=ArmISA
|
|
eventq_index=0
|
|
fpsid=1090793632
|
|
id_aa64afr0_el1=0
|
|
id_aa64afr1_el1=0
|
|
id_aa64dfr0_el1=1052678
|
|
id_aa64dfr1_el1=0
|
|
id_aa64isar0_el1=0
|
|
id_aa64isar1_el1=0
|
|
id_aa64mmfr0_el1=15728642
|
|
id_aa64mmfr1_el1=0
|
|
id_aa64pfr0_el1=17
|
|
id_aa64pfr1_el1=0
|
|
id_isar0=34607377
|
|
id_isar1=34677009
|
|
id_isar2=555950401
|
|
id_isar3=17899825
|
|
id_isar4=268501314
|
|
id_isar5=0
|
|
id_mmfr0=270536963
|
|
id_mmfr1=0
|
|
id_mmfr2=19070976
|
|
id_mmfr3=34611729
|
|
id_pfr0=49
|
|
id_pfr1=4113
|
|
midr=1091551472
|
|
system=system
|
|
|
|
[system.cpu.istage2_mmu]
|
|
type=ArmStage2MMU
|
|
children=stage2_tlb
|
|
eventq_index=0
|
|
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
|
tlb=system.cpu.itb
|
|
|
|
[system.cpu.istage2_mmu.stage2_tlb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=true
|
|
size=32
|
|
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|
|
|
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=true
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[4]
|
|
|
|
[system.cpu.itb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=false
|
|
size=64
|
|
walker=system.cpu.itb.walker
|
|
|
|
[system.cpu.itb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=false
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[2]
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=20
|
|
is_top_level=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
sequential_access=false
|
|
size=2097152
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=20
|
|
sequential_access=false
|
|
size=2097152
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentBus
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=parser 2.1.dict -batch
|
|
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
|
egid=100
|
|
env=
|
|
errout=cerr
|
|
euid=100
|
|
eventq_index=0
|
|
executable=/dist/cpu2000/binaries/arm/linux/parser
|
|
gid=100
|
|
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
|
max_stack_size=67108864
|
|
output=cout
|
|
pid=100
|
|
ppid=99
|
|
simpoint=114600000000
|
|
system=system
|
|
uid=100
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
eventq_index=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
master=system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side
|
|
|
|
[system.physmem]
|
|
type=SimpleDRAM
|
|
activation_limit=4
|
|
addr_mapping=RaBaChCo
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
devices_per_rank=8
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
mem_sched_policy=frfcfs
|
|
null=false
|
|
page_policy=open
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCL=13750
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=300000
|
|
tRP=13750
|
|
tRRD=6250
|
|
tWTR=7500
|
|
tXAW=40000
|
|
write_buffer_size=32
|
|
write_high_thresh_perc=70
|
|
write_low_thresh_perc=0
|
|
port=system.membus.master[0]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|