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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
Andreas Hansson d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.914421 # Number of seconds simulated
sim_ticks 1914420945000 # Number of ticks simulated
final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1299276 # Simulator instruction rate (inst/s)
host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44286723014 # Simulator tick rate (ticks/s)
host_mem_usage 288696 # Number of bytes of host memory used
host_seconds 43.23 # Real time elapsed on the host
sim_insts 56164879 # Number of instructions simulated
sim_ops 56164879 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory
system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory
system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory
system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.347664 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9062432 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.write_hits 6354530 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.data_hits 15416962 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.itb.fetch_hits 4974475 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
system.cpu.itb.fetch_accesses 4979481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 3828841890 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56164879 # Number of instructions committed
system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
system.cpu.num_func_calls 1482804 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls
system.cpu.num_int_insts 52037464 # number of integer instructions
system.cpu.num_fp_insts 324393 # number of float instructions
system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read
system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
system.cpu.num_mem_refs 15469580 # number of memory refs
system.cpu.num_load_insts 9099291 # Number of load instructions
system.cpu.num_store_insts 6370289 # Number of store instructions
system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles
system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles
system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.937415 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192901 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 927876 # number of replacements
system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use
system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55248171 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55248171 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55248171 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55248171 # number of overall hits
system.cpu.icache.overall_hits::total 55248171 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 928547 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 928547 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 928547 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 928547 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928547 # number of overall misses
system.cpu.icache.overall_misses::total 928547 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12629515000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12629515000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12629515000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12629515000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12629515000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12629515000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56176718 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56176718 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56176718 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 56176718 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 56176718 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 56176718 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016529 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016529 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016529 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016529 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016529 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016529 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13601.373975 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13601.373975 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13601.373975 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13601.373975 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928547 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 928547 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 928547 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 928547 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 928547 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 928547 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10772421000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10772421000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10772421000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10772421000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10772421000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10772421000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016529 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016529 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016529 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11601.373975 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11601.373975 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1390620 # number of replacements
system.cpu.dcache.tagsinuse 511.980059 # Cycle average of tags in use
system.cpu.dcache.total_refs 14044869 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1391132 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.096000 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 99394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.980059 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 7812084 # number of ReadReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 182982 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 182982 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits
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system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses
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system.cpu.dcache.ReadReq_miss_latency::total 25328737500 # number of ReadReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227305000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 227305000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 34195498000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 34195498000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 8881562 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15036509 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 15036509 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.120416 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086264 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.091369 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.091369 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23683.271185 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23683.271185 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29128.935239 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29128.935239 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13158.031838 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13158.031838 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24889.817487 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24889.817487 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::writebacks 835360 # number of writebacks
system.cpu.dcache.writebacks::total 835360 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::total 1069478 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1373875 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373875 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 1373875 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23189781500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23189781500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 192755000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 192755000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31447748000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31447748000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31447748000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424905500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424905500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011694000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011694000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3436599500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3436599500 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120416 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086264 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086264 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091369 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091369 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21683.271185 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21683.271185 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27128.935239 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27128.935239 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11158.031838 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11158.031838 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 336256 # number of replacements
system.cpu.l2cache.tagsinuse 65309.148086 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2447127 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 401418 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.096206 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 5907030000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 55687.812663 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4769.025398 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4852.310026 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.849729 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.data 814783 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1730020 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 835360 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 835360 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 187521 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187521 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 1002304 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 1002304 # number of overall hits
system.cpu.l2cache.overall_hits::total 1917541 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 271970 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses
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system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 116859 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 116859 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 388829 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
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system.cpu.l2cache.overall_misses::total 402119 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691484000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147953500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14839437500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 248500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077611500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6077611500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 691484000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20225565000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20917049000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 691484000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20225565000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20917049000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928527 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1086753 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2015280 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 835360 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 835360 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304380 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304380 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 928527 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1391133 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2319660 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 928527 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1391133 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2319660 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014313 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.141549 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383925 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383925 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014313 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279505 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.173353 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014313 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279505 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.173353 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52030.398796 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52020.272457 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52020.744233 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19115.384615 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19115.384615 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52008.073833 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52008.073833 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52017.062113 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52017.062113 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks
system.cpu.l2cache.writebacks::total 74188 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271970 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116859 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116859 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 388829 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 402119 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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