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gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.201852 # Number of seconds simulated
sim_ticks 201852280500 # Number of ticks simulated
final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 135871 # Simulator instruction rate (inst/s)
host_op_rate 153059 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53886430 # Simulator tick rate (ticks/s)
host_mem_usage 232836 # Number of bytes of host memory used
host_seconds 3745.88 # Real time elapsed on the host
sim_insts 508955133 # Number of instructions simulated
sim_ops 573341693 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory
system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory
system.physmem.bytes_written::total 6679360 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3419 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 156498 # Number of read requests responded to by this memory
system.physmem.num_reads::total 159917 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 104365 # Number of write requests responded to by this memory
system.physmem.num_writes::total 104365 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1084040 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 49619811 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50703851 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1084040 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1084040 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 33090337 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 33090337 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 33090337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1084040 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 49619811 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 83794188 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 403704562 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 183613146 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 143294212 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 7789120 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 98042390 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 90143773 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 12795154 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 116199 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 119018383 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 771038085 # Number of instructions fetch has processed
system.cpu.fetch.Branches 183613146 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 102938927 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 173093371 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 37034444 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 81728576 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 114776707 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2639607 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 402291353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.154621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.975773 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 229210831 56.98% 56.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 14330362 3.56% 60.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 23398991 5.82% 66.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22962860 5.71% 72.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 20943651 5.21% 77.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13279878 3.30% 80.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 13299573 3.31% 83.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 12124758 3.01% 86.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 52740449 13.11% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 402291353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.454821 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.909907 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 129139991 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 76355942 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 163648868 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4771100 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 28375452 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 26593121 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 78321 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 842377409 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 313716 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 28375452 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 137010485 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5387793 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 57527480 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 160406240 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 13583903 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 812203916 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 883 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2847047 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 7163226 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 967528997 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3555884446 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3555882861 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 295328850 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3042535 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3042531 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 44411709 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 172477044 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 75019988 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 27139166 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 14058077 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 762853534 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4467400 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 672309193 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 402291353 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 436530 4.38% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 6785214 68.04% 72.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2750735 27.58% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 451600936 67.17% 67.17% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 386071 0.06% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 155208445 23.09% 90.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 65113622 9.69% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 672309193 # Type of FU issued
system.cpu.iq.rate 1.665350 # Inst issue rate
system.cpu.iq.fu_busy_cnt 9972479 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014833 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1758479254 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 960016621 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 651381097 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 682281537 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 8428766 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 45704007 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 43585 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 806080 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 17416029 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 19464 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1080 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 28375452 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1989251 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 96453 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 768887058 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1243291 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172477044 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 75019988 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2978672 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 38122 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5312 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 806080 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4756345 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4163931 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8920276 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 661932492 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 151574229 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10376701 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1566124 # number of nop insts executed
system.cpu.iew.exec_refs 215230219 # number of memory reference insts executed
system.cpu.iew.exec_branches 139385144 # Number of branches executed
system.cpu.iew.exec_stores 63655990 # Number of stores executed
system.cpu.iew.exec_rate 1.639646 # Inst execution rate
system.cpu.iew.wb_sent 656632887 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 651381113 # cumulative count of insts written-back
system.cpu.iew.wb_producers 375930281 # num instructions producing a value
system.cpu.iew.wb_consumers 649035735 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.613509 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.579214 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 194215600 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 7713933 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 373915902 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.536938 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.196487 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 161102013 43.09% 43.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 102670077 27.46% 70.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 34449601 9.21% 79.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 18433917 4.93% 84.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 17480337 4.67% 89.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7750601 2.07% 91.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6975147 1.87% 93.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3144360 0.84% 94.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 21909849 5.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 373915902 # Number of insts commited each cycle
system.cpu.commit.committedInsts 510299017 # Number of instructions committed
system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 184376996 # Number of memory references committed
system.cpu.commit.loads 126773037 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 122291783 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 473701621 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.bw_lim_events 21909849 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1120900092 # The number of ROB reads
system.cpu.rob.rob_writes 1566319482 # The number of ROB writes
system.cpu.timesIdled 51224 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1413209 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 508955133 # Number of Instructions Simulated
system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated
system.cpu.cpi 0.793203 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.793203 # CPI: Total CPI of All Threads
system.cpu.ipc 1.260712 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.260712 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3088645957 # number of integer regfile reads
system.cpu.int_regfile_writes 759574381 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 999041226 # number of misc regfile reads
system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes
system.cpu.icache.replacements 15551 # number of replacements
system.cpu.icache.tagsinuse 1091.493459 # Cycle average of tags in use
system.cpu.icache.total_refs 114757583 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 17412 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 6590.718068 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1091.493459 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.532956 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.532956 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 114757583 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 114757583 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 114757583 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 114757583 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 114757583 # number of overall hits
system.cpu.icache.overall_hits::total 114757583 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19124 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19124 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19124 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19124 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19124 # number of overall misses
system.cpu.icache.overall_misses::total 19124 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 228709500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 228709500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 228709500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 228709500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 228709500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 228709500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 114776707 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 114776707 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 114776707 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 114776707 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 114776707 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 114776707 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000167 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000167 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000167 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000167 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000167 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000167 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11959.291989 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 11959.291989 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 11959.291989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 11959.291989 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1676 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1676 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1676 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1676 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1676 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1676 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17448 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 17448 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 17448 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 17448 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 17448 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 17448 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154473000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 154473000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154473000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 154473000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154473000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 154473000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000152 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000152 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000152 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8853.335626 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8853.335626 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1187048 # number of replacements
system.cpu.dcache.tagsinuse 4054.257449 # Cycle average of tags in use
system.cpu.dcache.total_refs 194842504 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1191144 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 163.575944 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 4633717000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4054.257449 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.989809 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.989809 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 137485453 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 137485453 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 52891890 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 52891890 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233029 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 2233029 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 2232023 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 2232023 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 190377343 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 190377343 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 190377343 # number of overall hits
system.cpu.dcache.overall_hits::total 190377343 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1221436 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1221436 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1347416 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1347416 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 47 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 47 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2568852 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2568852 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2568852 # number of overall misses
system.cpu.dcache.overall_misses::total 2568852 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9648379000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9648379000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23124597500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23124597500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 412500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 412500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 32772976500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 32772976500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 32772976500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 32772976500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 138706889 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 138706889 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233076 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 2233076 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232023 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 2232023 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 192946195 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 192946195 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 192946195 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 192946195 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008806 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.008806 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024842 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024842 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000021 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000021 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.013314 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013314 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013314 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013314 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7899.209619 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 7899.209619 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17162.181168 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks
system.cpu.dcache.writebacks::total 1101507 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 47 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1377669 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1377669 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1377669 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1377669 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843084 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 843084 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348099 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 348099 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1191183 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1191183 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1191183 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1191183 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3511124500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3511124500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4141906500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4141906500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7653031000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7653031000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7653031000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7653031000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006078 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006078 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006174 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006174 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4164.620014 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4164.620014 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11898.645213 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11898.645213 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 128736 # number of replacements
system.cpu.l2cache.tagsinuse 26456.309379 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1725132 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 159966 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 10.784367 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 105169103500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 22633.637803 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 309.674133 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 3512.997443 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.690724 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.009451 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.107208 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.807382 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 13983 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 789454 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 803437 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1101507 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1101507 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 245171 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 245171 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 13983 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1034625 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1048608 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 13983 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1034625 # number of overall hits
system.cpu.l2cache.overall_hits::total 1048608 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3427 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 53077 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 56504 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 103442 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 103442 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3427 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 156519 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 159946 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3427 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 156519 # number of overall misses
system.cpu.l2cache.overall_misses::total 159946 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 122356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1846533500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1968889500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3549540000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3549540000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 122356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5396073500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 5518429500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 122356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5396073500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 5518429500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 17410 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 842531 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 859941 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1101507 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1101507 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 39 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 39 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 348613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 348613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 17410 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1191144 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1208554 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 17410 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1191144 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1208554 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.196841 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062997 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.065707 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.102564 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.102564 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296724 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.296724 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.196841 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.131402 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.132345 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.196841 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.131402 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.132345 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35703.530785 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34789.711174 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34845.134858 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.301734 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.301734 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35703.530785 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34475.517349 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34501.828742 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35703.530785 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34475.517349 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34501.828742 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 104365 # number of writebacks
system.cpu.l2cache.writebacks::total 104365 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3419 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53056 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 56475 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103442 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 103442 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3419 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 156498 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 159917 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3419 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 156498 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 159917 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111443000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1678392000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1789835000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3216081000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3216081000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111443000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4894473000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5005916000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111443000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4894473000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5005916000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.062972 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065673 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.102564 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.102564 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296724 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296724 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.132321 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.132321 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32595.203276 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31634.348613 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31692.518814 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31090.669167 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31090.669167 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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