183 lines
7.4 KiB
C++
183 lines
7.4 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//Include the definitions of the micro ops.
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//These are python representations of static insts which stand on their own
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//and make up an internal instruction set. They are used by the micro
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//assembler.
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##include "microops/microops.isa"
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//Include code to build macroops in both C++ and python.
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##include "macroop.isa"
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let {{
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import sys
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sys.path[0:0] = ["src/arch/x86/isa/"]
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from insts import microcode
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# print microcode
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from micro_asm import MicroAssembler, Rom_Macroop, Rom
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mainRom = Rom('main ROM')
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assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
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# Add in symbols for the microcode registers
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for num in range(15):
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assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
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for num in range(7):
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assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
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# Add in symbols for the segment descriptor registers
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for letter in ("C", "D", "E", "F", "G", "S"):
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assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
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for reg in ("TR", "IDTR"):
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assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
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for reg in ("TSL", "TSG"):
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assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
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# Miscellaneous symbols
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symbols = {
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"reg" : "env.reg",
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"xmml" : "FLOATREG_XMM_LOW(env.reg)",
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"xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
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"regm" : "env.regm",
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"xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
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"xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
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"imm" : "adjustedImm",
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"disp" : "adjustedDisp",
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"seg" : "env.seg",
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"scale" : "env.scale",
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"index" : "env.index",
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"base" : "env.base",
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"dsz" : "env.dataSize",
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"asz" : "env.addressSize",
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"ssz" : "env.stackSize"
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}
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assembler.symbols.update(symbols)
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assembler.symbols["ldsz"] = \
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"((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
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assembler.symbols["lasz"] = \
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"((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
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assembler.symbols["lssz"] = \
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"((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
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# Short hand for common scale-index-base combinations.
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assembler.symbols["sib"] = \
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[symbols["scale"], symbols["index"], symbols["base"]]
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assembler.symbols["riprel"] = \
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["1", assembler.symbols["t0"], assembler.symbols["t7"]]
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# This segment selects an internal address space mapped to MSRs,
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# CPUID info, etc.
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assembler.symbols["intseg"] = "SEGMENT_REG_MS"
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# This segment always has base 0, and doesn't imply any special handling
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# like the internal segment above
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assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
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for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
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assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
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for reg in range(15):
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assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
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for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
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assembler.symbols[flag] = flag + "Bit"
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for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
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'MSTRZ', 'STRZ', 'MSTRC',
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'OF', 'CF', 'ZF', 'CvZF',
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'SF', 'PF', 'SxOF', 'SxOvZF'):
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assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
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assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
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assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
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assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
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assembler.symbols["CTrue"] = "ConditionTests::True"
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assembler.symbols["CFalse"] = "ConditionTests::False"
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# Code literal which forces a default 64 bit operand size in 64 bit mode.
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assembler.symbols["oszIn64Override"] = '''
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if (machInst.mode.submode == SixtyFourBitMode &&
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env.dataSize == 4)
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env.dataSize = 8;
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'''
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assembler.symbols["oszForPseudoDesc"] = '''
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if (machInst.mode.submode == SixtyFourBitMode)
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env.dataSize = 8;
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else
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env.dataSize = 4;
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'''
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def trimImm(width):
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return "adjustedImm = adjustedImm & mask(%s);" % width
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assembler.symbols["trimImm"] = trimImm
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def labeler(labelStr):
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return "label_%s" % labelStr
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assembler.symbols["label"] = labeler
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def stack_index(index):
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return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
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assembler.symbols["st"] = stack_index
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macroopDict = assembler.assemble(microcode)
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}};
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