48d4ca522a
Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes).
440 lines
46 KiB
Text
440 lines
46 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
host_inst_rate 213847 # Simulator instruction rate (inst/s)
|
|
host_mem_usage 218620 # Number of bytes of host memory used
|
|
host_seconds 372.19 # Real time elapsed on the host
|
|
host_tick_rate 72905538 # Simulator tick rate (ticks/s)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
sim_insts 79591756 # Number of instructions simulated
|
|
sim_seconds 0.027135 # Number of seconds simulated
|
|
sim_ticks 27134794500 # Number of ticks simulated
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits
|
|
system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
|
|
system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
|
|
system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
|
|
system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
|
|
system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups
|
|
system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
|
|
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
|
system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
|
system.cpu.commit.COM:committed_per_cycle.samples 51751169
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
|
0 22506446 4348.97%
|
|
1 11357579 2194.65%
|
|
2 5114502 988.29%
|
|
3 3560855 688.07%
|
|
4 2552504 493.23%
|
|
5 1532717 296.17%
|
|
6 1008933 194.96%
|
|
7 796739 153.96%
|
|
8 3320894 641.70%
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
system.cpu.commit.COM:count 88340672 # Number of instructions committed
|
|
system.cpu.commit.COM:loads 20379399 # Number of loads committed
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
|
|
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit
|
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
|
|
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
|
system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks.
|
|
system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_hits 33838925 # number of overall hits
|
|
system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_misses 1199965 # number of overall misses
|
|
system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.replacements 200933 # number of replacements
|
|
system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.writebacks 147760 # number of writebacks
|
|
system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked
|
|
system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch
|
|
system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode
|
|
system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle
|
|
system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running
|
|
system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
|
|
system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
|
|
system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
|
|
system.cpu.dtb.data_accesses 36599689 # DTB accesses
|
|
system.cpu.dtb.data_acv 39 # DTB access violations
|
|
system.cpu.dtb.data_hits 36425481 # DTB hits
|
|
system.cpu.dtb.data_misses 174208 # DTB misses
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.read_accesses 21541288 # DTB read accesses
|
|
system.cpu.dtb.read_acv 37 # DTB read access violations
|
|
system.cpu.dtb.read_hits 21383020 # DTB read hits
|
|
system.cpu.dtb.read_misses 158268 # DTB read misses
|
|
system.cpu.dtb.write_accesses 15058401 # DTB write accesses
|
|
system.cpu.dtb.write_acv 2 # DTB write access violations
|
|
system.cpu.dtb.write_hits 15042461 # DTB write hits
|
|
system.cpu.dtb.write_misses 15940 # DTB write misses
|
|
system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered
|
|
system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
|
|
system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
|
|
system.cpu.fetch.SquashCycles 567637 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
|
|
system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist.samples 53041270
|
|
system.cpu.fetch.rateDist.min_value 0
|
|
0 33206277 6260.46%
|
|
1 1871594 352.86%
|
|
2 1529415 288.34%
|
|
3 1809626 341.17%
|
|
4 3985239 751.35%
|
|
5 1867239 352.04%
|
|
6 695846 131.19%
|
|
7 1111736 209.60%
|
|
8 6964298 1313.00%
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits 13297366 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 88706 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements 83888 # number of replacements
|
|
system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 14745486 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 15291392 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 32396987 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
IntAlu 47898565 56.12% # Type of FU issued
|
|
IntMult 42953 0.05% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 121655 0.14% # Type of FU issued
|
|
FloatCmp 88 0.00% # Type of FU issued
|
|
FloatCvt 122104 0.14% # Type of FU issued
|
|
FloatMult 53 0.00% # Type of FU issued
|
|
FloatDiv 38535 0.05% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 21753622 25.49% # Type of FU issued
|
|
MemWrite 15368770 18.01% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 97100 9.91% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 470602 48.04% # attempts to use FU when none available
|
|
MemWrite 411938 42.05% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 53041270
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333
|
|
system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 13412237 # ITB accesses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_hits 13386072 # ITB hits
|
|
system.cpu.itb.fetch_misses 26165 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 102894 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 188071 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 148779 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 120647 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 54269590 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|