gem5/src/arch/x86/isa/microops
Andreas Sandberg 654d1e675a x86: Add support for loading 32-bit and 80-bit floats in the x87
The x87 FPU supports three floating point formats: 32-bit, 64-bit, and
80-bit floats. The current gem5 implementation supports 32-bit and
64-bit floats, but only works correctly for 64-bit floats. This
changeset fixes the 32-bit float handling by correctly loading and
rounding (using truncation) 32-bit floats instead of simply truncating
the bit pattern.

80-bit floats are loaded by first loading the 80-bits of the float to
two temporary integer registers. A micro-op (cvtint_fp80) then
converts the contents of the two integer registers to the internal FP
representation (double). Similarly, when storing an 80-bit float,
there are two conversion routines (ctvfp80h_int and cvtfp80l_int) that
convert an internal FP register to 80-bit and stores the upper 64-bits
or lower 32-bits to an integer register, which is the written to
memory using normal integer stores.
2013-09-30 12:00:20 +02:00
..
base.isa GCC: Get everything working with gcc 4.6.1. 2011-10-31 01:09:44 -07:00
debug.isa x86: Add a separate register for D flag bit 2012-09-11 09:25:43 -05:00
fpop.isa x86: Add support for loading 32-bit and 80-bit floats in the x87 2013-09-30 12:00:20 +02:00
ldstop.isa x86: Add support for loading 32-bit and 80-bit floats in the x87 2013-09-30 12:00:20 +02:00
limmop.isa x86: Fix loading of floating point constants 2013-06-18 16:30:06 +02:00
mediaop.isa x86: implements emms instruction 2013-01-15 07:43:20 -06:00
microops.isa copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
regop.isa x86: add op class for int and fp microops in isa description 2013-05-21 11:33:57 -05:00
seqop.isa x86: Add a separate register for D flag bit 2012-09-11 09:25:43 -05:00
specop.isa x86: Add a separate register for D flag bit 2012-09-11 09:25:43 -05:00