689cab36c9
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
188 lines
6.1 KiB
C++
188 lines
6.1 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_ALPHA_CPU_HH__
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#define __CPU_O3_ALPHA_CPU_HH__
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#include "arch/regfile.hh"
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#include "arch/types.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/o3/cpu.hh"
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#include "sim/byteswap.hh"
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class EndQuiesceEvent;
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namespace Kernel {
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class Statistics;
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};
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class TranslatingPort;
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/**
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* AlphaO3CPU class. Derives from the FullO3CPU class, and
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* implements all ISA and implementation specific functions of the
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* CPU. This is the CPU class that is used for the SimObjects, and is
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* what is given to the DynInsts. Most of its state exists in the
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* FullO3CPU; the state is has is mainly for ISA specific
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* functionality.
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*/
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template <class Impl>
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class AlphaO3CPU : public FullO3CPU<Impl>
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{
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public:
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typedef O3ThreadState<Impl> ImplState;
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typedef O3ThreadState<Impl> Thread;
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typedef typename Impl::Params Params;
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/** Constructs an AlphaO3CPU with the given parameters. */
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AlphaO3CPU(Params *params);
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/** Registers statistics. */
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void regStats();
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#if FULL_SYSTEM
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/** Translates instruction requestion. */
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Fault translateInstReq(RequestPtr &req, Thread *thread)
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{
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return this->itb->translate(req, thread->getTC());
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}
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/** Translates data read request. */
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Fault translateDataReadReq(RequestPtr &req, Thread *thread)
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{
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return this->dtb->translate(req, thread->getTC(), false);
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}
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/** Translates data write request. */
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Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
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{
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return this->dtb->translate(req, thread->getTC(), true);
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}
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#else
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/** Translates instruction requestion in syscall emulation mode. */
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Fault translateInstReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data read request in syscall emulation mode. */
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Fault translateDataReadReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data write request in syscall emulation mode. */
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Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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#endif
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/** Reads a miscellaneous register. */
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TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
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/** Sets a miscellaneous register. */
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void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
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unsigned tid);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
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unsigned tid);
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/** Initiates a squash of all in-flight instructions for a given
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* thread. The source of the squash is an external update of
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* state through the TC.
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*/
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void squashFromTC(unsigned tid);
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#if FULL_SYSTEM
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/** Posts an interrupt. */
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void post_interrupt(int int_num, int index);
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/** HW return from error interrupt. */
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Fault hwrei(unsigned tid);
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bool simPalCheck(int palFunc, unsigned tid);
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/** Returns the Fault for any valid interrupt. */
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Fault getInterrupts();
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/** Processes any an interrupt fault. */
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void processInterrupts(Fault interrupt);
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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#endif
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/** Traps to handle given fault. */
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void trap(Fault fault, unsigned tid);
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#if !FULL_SYSTEM
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/** Executes a syscall.
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* @todo: Determine if this needs to be virtual.
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*/
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void syscall(int64_t callnum, int tid);
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/** Gets a syscall argument. */
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TheISA::IntReg getSyscallArg(int i, int tid);
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/** Used to shift args for indirect syscall. */
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void setSyscallArg(int i, TheISA::IntReg val, int tid);
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/** Sets the return value of a syscall. */
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void setSyscallReturn(SyscallReturn return_value, int tid);
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#endif
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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Fault read(RequestPtr &req, T &data, int load_idx)
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{
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return this->iew.ldstQueue.read(req, data, load_idx);
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}
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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Fault write(RequestPtr &req, T &data, int store_idx)
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{
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return this->iew.ldstQueue.write(req, data, store_idx);
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}
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Addr lockAddr;
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/** Temporary fix for the lock flag, works in the UP case. */
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bool lockFlag;
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};
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#endif // __CPU_O3_ALPHA_CPU_HH__
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