349 lines
39 KiB
Text
349 lines
39 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.765623 # Number of seconds simulated
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sim_ticks 765623032000 # Number of ticks simulated
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final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 835603 # Simulator instruction rate (inst/s)
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host_op_rate 835603 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1062971026 # Simulator tick rate (ticks/s)
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host_mem_usage 214568 # Number of bytes of host memory used
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host_seconds 720.27 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 5889984 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3797824 # Number of bytes written to this memory
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system.physmem.num_reads 92031 # Number of read requests responded to by this memory
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system.physmem.num_writes 59341 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 114514042 # DTB read hits
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system.cpu.dtb.read_misses 2631 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 114516673 # DTB read accesses
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system.cpu.dtb.write_hits 39451321 # DTB write hits
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system.cpu.dtb.write_misses 2302 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 39453623 # DTB write accesses
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system.cpu.dtb.data_hits 153965363 # DTB hits
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system.cpu.dtb.data_misses 4933 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 153970296 # DTB accesses
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system.cpu.itb.fetch_hits 601861898 # ITB hits
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system.cpu.itb.fetch_misses 20 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 601861918 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 1531246064 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 601856964 # Number of instructions committed
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system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
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system.cpu.num_func_calls 2395217 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
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system.cpu.num_int_insts 563959696 # number of integer instructions
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system.cpu.num_fp_insts 1520 # number of float instructions
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system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
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system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
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system.cpu.num_mem_refs 153970296 # number of memory refs
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system.cpu.num_load_insts 114516673 # Number of load instructions
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system.cpu.num_store_insts 39453623 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 24 # number of replacements
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system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
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system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits
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system.cpu.icache.overall_hits::total 601861103 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
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system.cpu.icache.overall_misses::total 795 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 451299 # number of replacements
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system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
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system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
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system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
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system.cpu.dcache.overall_misses::total 455395 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
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system.cpu.dcache.writebacks::total 408190 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 73734 # number of replacements
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system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits
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system.cpu.l2cache.overall_hits::total 364159 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 92031 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59341 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|