62fa781fee
object defined there was renamed Root long ago).
SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/stats/events.cc:
base/trace.hh:
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/inst_queue_impl.hh:
cpu/pc_event.cc:
cpu/static_inst.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
sim/builder.cc:
sim/eventq.cc:
sim/main.cc:
sim/root.cc:
sim/stat_control.cc:
Rename sim/universe.{cc,hh} to root.{cc,hh}.
--HG--
rename : sim/universe.cc => sim/root.cc
extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
88 lines
3 KiB
C++
88 lines
3 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <iostream>
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#include "cpu/static_inst.hh"
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#include "sim/root.hh"
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template <class ISA>
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StaticInstPtr<ISA> StaticInst<ISA>::nullStaticInstPtr;
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template <class ISA>
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typename StaticInst<ISA>::DecodeCache StaticInst<ISA>::decodeCache;
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// Define the decode cache hash map.
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template StaticInst<AlphaISA>::DecodeCache
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StaticInst<AlphaISA>::decodeCache;
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template <class ISA>
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void
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StaticInst<ISA>::dumpDecodeCacheStats()
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{
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using namespace std;
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cerr << "Decode hash table stats @ " << curTick << ":" << endl;
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cerr << "\tnum entries = " << decodeCache.size() << endl;
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cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
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vector<int> hist(100, 0);
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int max_hist = 0;
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for (int i = 0; i < decodeCache.bucket_count(); ++i) {
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int count = decodeCache.elems_in_bucket(i);
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if (count > max_hist)
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max_hist = count;
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hist[count]++;
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}
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for (int i = 0; i <= max_hist; ++i) {
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cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
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}
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}
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template StaticInstPtr<AlphaISA>
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StaticInst<AlphaISA>::nullStaticInstPtr;
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template <class ISA>
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bool
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StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
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{
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if (isDirectCtrl()) {
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tgt = branchTarget(pc);
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return true;
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}
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if (isIndirectCtrl()) {
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tgt = branchTarget(xc);
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return true;
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}
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return false;
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}
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// force instantiation of template function(s) above
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template class StaticInst<AlphaISA>;
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