61d95de4c8
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
197 lines
5.1 KiB
C++
197 lines
5.1 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __KERNEL_STATS_HH__
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#define __KERNEL_STATS_HH__
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#include <map>
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#include <stack>
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#include <string>
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#include <vector>
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#include "base/statistics.hh"
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#include "sim/serialize.hh"
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#include "targetarch/isa_traits.hh"
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class BaseCPU;
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class ExecContext;
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class FnEvent;
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// What does kernel stats expect is included?
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class StaticInstBase;
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class System;
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enum Fault;
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namespace Kernel {
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enum cpu_mode { kernel, user, idle, interrupt, cpu_mode_num };
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extern const char *modestr[];
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class Binning
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{
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private:
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std::string myname;
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System *system;
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private:
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// lisa's binning stuff
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struct fnCall
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{
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Stats::MainBin *myBin;
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std::string name;
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};
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struct SWContext
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{
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Counter calls;
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std::stack<fnCall *> callStack;
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};
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std::map<const std::string, Stats::MainBin *> fnBins;
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std::map<const Addr, SWContext *> swCtxMap;
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std::multimap<const std::string, std::string> callerMap;
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void populateMap(std::string caller, std::string callee);
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std::vector<FnEvent *> fnEvents;
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Stats::Scalar<> fnCalls;
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Stats::MainBin *getBin(const std::string &name);
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bool findCaller(std::string, std::string) const;
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SWContext *findContext(Addr pcb);
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bool addContext(Addr pcb, SWContext *ctx)
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{
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return (swCtxMap.insert(std::make_pair(pcb, ctx))).second;
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}
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void remContext(Addr pcb)
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{
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swCtxMap.erase(pcb);
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}
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void dumpState() const;
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SWContext *swctx;
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std::vector<std::string> binned_fns;
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private:
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Stats::MainBin *modeBin[cpu_mode_num];
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public:
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const bool bin;
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const bool fnbin;
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cpu_mode themode;
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void palSwapContext(ExecContext *xc);
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void execute(ExecContext *xc, const StaticInstBase *inst);
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void call(ExecContext *xc, Stats::MainBin *myBin);
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void changeMode(cpu_mode mode);
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public:
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Binning(System *sys);
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virtual ~Binning();
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const std::string name() const { return myname; }
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void regStats(const std::string &name);
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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class Statistics : public Serializable
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{
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friend class Binning;
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private:
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std::string myname;
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ExecContext *xc;
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Addr idleProcess;
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cpu_mode themode;
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Tick lastModeTick;
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bool bin_int;
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void changeMode(cpu_mode newmode);
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private:
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Stats::Scalar<> _arm;
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Stats::Scalar<> _quiesce;
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Stats::Scalar<> _ivlb;
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Stats::Scalar<> _ivle;
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Stats::Scalar<> _hwrei;
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Stats::Vector<> _iplCount;
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Stats::Vector<> _iplGood;
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Stats::Vector<> _iplTicks;
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Stats::Formula _iplUsed;
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Stats::Vector<> _callpal;
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Stats::Vector<> _syscall;
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Stats::Vector<> _faults;
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Stats::Vector<> _mode;
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Stats::Vector<> _modeGood;
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Stats::Formula _modeFraction;
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Stats::Vector<> _modeTicks;
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Stats::Scalar<> _swap_context;
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private:
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int iplLast;
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Tick iplLastTick;
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public:
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Statistics(ExecContext *context);
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const std::string name() const { return myname; }
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void regStats(const std::string &name);
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public:
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void arm() { _arm++; }
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void quiesce() { _quiesce++; }
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void ivlb() { _ivlb++; }
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void ivle() { _ivle++; }
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void hwrei() { _hwrei++; }
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void fault(Fault fault) { _faults[fault]++; }
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void swpipl(int ipl);
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void mode(cpu_mode newmode);
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void context(Addr oldpcbb, Addr newpcbb);
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void callpal(int code);
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void setIdleProcess(Addr idle);
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/* end namespace Kernel */ }
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#endif // __KERNEL_STATS_HH__
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