Nikos Nikoleris 61860f2419 cpu: Change traffic generators to use different values for writes ... Previously all traffic generators would use the same value for write requests. With this change traffic generators use their master id as the payload of write requests making them more useful for the memchecker. Change-Id: Id1a6b8f02853789b108ef6003f4c32ab929bb123 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>		2016-12-05 16:48:20 -05:00
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arch	hsail: disable asserts to allow immediate operands i.e. 0 with loads	2016-12-02 18:01:58 -05:00
base	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	2016-11-30 17:10:28 -05:00
cpu	cpu: Change traffic generators to use different values for writes	2016-12-05 16:48:20 -05:00
dev	dev: Fix buffer length when unserializing an eth pkt	2016-11-29 13:04:45 -05:00
doc	sim: Adding support for power models	2016-06-06 17:16:44 +01:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
gpu-compute	hsail: remove the panic guarding function directives	2016-12-02 18:01:42 -05:00
kern	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
mem	mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv	2016-12-05 16:48:19 -05:00
proto	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
python	base: eliminate ipython warning	2016-09-15 18:21:38 +01:00
sim	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	2016-11-30 17:10:28 -05:00
unittest	style: remove trailing whitespace	2016-02-06 17:21:18 -08:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: fix sanitizer flags with multiple sanitizers	2016-11-28 12:44:54 -05:00