1193 lines
137 KiB
Text
1193 lines
137 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.920428 # Number of seconds simulated
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sim_ticks 1920428041000 # Number of ticks simulated
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final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1405906 # Simulator instruction rate (inst/s)
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host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48056353161 # Simulator tick rate (ticks/s)
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host_mem_usage 307800 # Number of bytes of host memory used
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host_seconds 39.96 # Real time elapsed on the host
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sim_insts 56182750 # Number of instructions simulated
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sim_ops 56182750 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 442968 # Number of read requests accepted
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system.physmem.writeReqs 115466 # Number of write requests accepted
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system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 27966 # Per bank write bursts
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system.physmem.perBankRdBursts::1 28089 # Per bank write bursts
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system.physmem.perBankRdBursts::2 28297 # Per bank write bursts
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system.physmem.perBankRdBursts::3 28053 # Per bank write bursts
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system.physmem.perBankRdBursts::4 27407 # Per bank write bursts
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system.physmem.perBankRdBursts::5 27545 # Per bank write bursts
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system.physmem.perBankRdBursts::6 26911 # Per bank write bursts
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system.physmem.perBankRdBursts::7 26762 # Per bank write bursts
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system.physmem.perBankRdBursts::8 27807 # Per bank write bursts
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system.physmem.perBankRdBursts::9 27255 # Per bank write bursts
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system.physmem.perBankRdBursts::10 27714 # Per bank write bursts
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system.physmem.perBankRdBursts::11 27327 # Per bank write bursts
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system.physmem.perBankRdBursts::12 27431 # Per bank write bursts
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system.physmem.perBankRdBursts::13 28073 # Per bank write bursts
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system.physmem.perBankRdBursts::14 28024 # Per bank write bursts
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system.physmem.perBankRdBursts::15 28256 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7722 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7593 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7833 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7543 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7010 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6469 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6223 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7224 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6661 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7099 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6780 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7009 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7722 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7773 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7817 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
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system.physmem.totGap 1920416169000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 442968 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 115466 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation
|
|
system.physmem.totQLat 6257775000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.15 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 419360 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 92763 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3438931.31 # Average gap between requests
|
|
system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.membus.throughput 18651952 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 292310 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 292310 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9650 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9650 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 115466 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 158141 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 158141 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 35784340 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9064966 # DTB read hits
|
|
system.cpu.dtb.read_misses 10312 # DTB read misses
|
|
system.cpu.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 728817 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6356267 # DTB write hits
|
|
system.cpu.dtb.write_misses 1140 # DTB write misses
|
|
system.cpu.dtb.write_acv 157 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 291929 # DTB write accesses
|
|
system.cpu.dtb.data_hits 15421233 # DTB hits
|
|
system.cpu.dtb.data_misses 11452 # DTB misses
|
|
system.cpu.dtb.data_acv 367 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1020746 # DTB accesses
|
|
system.cpu.itb.fetch_hits 4973920 # ITB hits
|
|
system.cpu.itb.fetch_misses 4997 # ITB misses
|
|
system.cpu.itb.fetch_acv 184 # ITB acv
|
|
system.cpu.itb.fetch_accesses 4978917 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 3840856082 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 56182750 # Number of instructions committed
|
|
system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
|
|
system.cpu.num_func_calls 1483342 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 52054772 # number of integer instructions
|
|
system.cpu.num_fp_insts 324326 # number of float instructions
|
|
system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 15473812 # number of memory refs
|
|
system.cpu.num_load_insts 9101789 # Number of load instructions
|
|
system.cpu.num_store_insts 6372023 # Number of store instructions
|
|
system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.934400 # Percentage of idle cycles
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192898 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1908
|
|
system.cpu.kern.mode_good::user 1739
|
|
system.cpu.kern.mode_good::idle 169
|
|
system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4176 # number of times the context was actually changed
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.throughput 1409150 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51202 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 2706172 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 928358 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 55265541 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 929029 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 336056 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1050 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4896 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 25947571 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 25947571 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 401915 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 73954 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1390568 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63152102 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63152102 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13666948 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1373840 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 835114 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency
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|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s)
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|
system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
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---------- End Simulation Statistics ----------
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