447 lines
51 KiB
Text
447 lines
51 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.647873 # Number of seconds simulated
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sim_ticks 1647872849000 # Number of ticks simulated
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final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 782951 # Simulator instruction rate (inst/s)
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host_op_rate 1447764 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1560332529 # Simulator tick rate (ticks/s)
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host_mem_usage 260992 # Number of bytes of host memory used
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host_seconds 1056.10 # Real time elapsed on the host
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sim_insts 826877110 # Number of instructions simulated
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sim_ops 1528988702 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
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system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 26154600 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 174452 # Transaction distribution
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system.membus.trans_dist::ReadResp 174452 # Transaction distribution
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system.membus.trans_dist::Writeback 292286 # Transaction distribution
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system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
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system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 43099456 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu.workload.num_syscalls 551 # Number of system calls
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system.cpu.numCycles 3295745698 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 826877110 # Number of instructions committed
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system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 35346287 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1526605510 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
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system.cpu.num_mem_refs 533262343 # number of memory refs
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system.cpu.num_load_insts 384102157 # Number of load instructions
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system.cpu.num_store_insts 149160186 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.tags.replacements 1253 # number of replacements
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system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
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system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
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system.cpu.icache.overall_misses::total 2814 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 348459 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits
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system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses
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system.cpu.l2cache.overall_misses::total 381143 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 292286 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2323523 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|