612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
328 lines
9.3 KiB
C++
328 lines
9.3 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_UTILITY_HH__
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#define __ARCH_ARM_UTILITY_HH__
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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class ArmSystem;
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namespace ArmISA {
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inline PCState
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buildRetPC(const PCState &curPC, const PCState &callPC)
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{
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PCState retPC = callPC;
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retPC.uEnd();
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return retPC;
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}
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inline bool
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testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
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{
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bool n = (nz & 0x2);
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bool z = (nz & 0x1);
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switch (code)
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{
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case COND_EQ: return z;
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case COND_NE: return !z;
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case COND_CS: return c;
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case COND_CC: return !c;
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case COND_MI: return n;
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case COND_PL: return !n;
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case COND_VS: return v;
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case COND_VC: return !v;
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case COND_HI: return (c && !z);
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case COND_LS: return !(c && !z);
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case COND_GE: return !(n ^ v);
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case COND_LT: return (n ^ v);
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case COND_GT: return !(n ^ v || z);
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case COND_LE: return (n ^ v || z);
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case COND_AL: return true;
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case COND_UC: return true;
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default:
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panic("Unhandled predicate condition: %d\n", code);
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}
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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inline void startupCPU(ThreadContext *tc, int cpuId)
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{
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tc->activate(Cycles(0));
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}
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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static inline void
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copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("Copy Misc. Regs Not Implemented Yet\n");
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}
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void initCPU(ThreadContext *tc, int cpuId);
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static inline bool
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inUserMode(CPSR cpsr)
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{
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return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
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}
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static inline bool
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inUserMode(ThreadContext *tc)
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{
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return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
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}
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static inline bool
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inPrivilegedMode(CPSR cpsr)
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{
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return !inUserMode(cpsr);
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}
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static inline bool
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inPrivilegedMode(ThreadContext *tc)
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{
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return !inUserMode(tc);
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}
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bool inAArch64(ThreadContext *tc);
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static inline OperatingMode
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currOpMode(ThreadContext *tc)
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{
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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return (OperatingMode) (uint8_t) cpsr.mode;
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}
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static inline ExceptionLevel
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currEL(ThreadContext *tc)
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{
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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return (ExceptionLevel) (uint8_t) cpsr.el;
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}
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bool ELIs64(ThreadContext *tc, ExceptionLevel el);
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bool isBigEndian64(ThreadContext *tc);
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/**
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* Removes the tag from tagged addresses if that mode is enabled.
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* @param addr The address to be purified.
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* @param tc The thread context.
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* @param el The controlled exception level.
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* @return The purified address.
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*/
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Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
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static inline bool
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inSecureState(SCR scr, CPSR cpsr)
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{
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switch ((OperatingMode) (uint8_t) cpsr.mode) {
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case MODE_MON:
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case MODE_EL3T:
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case MODE_EL3H:
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return true;
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case MODE_HYP:
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case MODE_EL2T:
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case MODE_EL2H:
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return false;
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default:
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return !scr.ns;
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}
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}
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bool longDescFormatInUse(ThreadContext *tc);
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bool inSecureState(ThreadContext *tc);
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uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
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static inline uint32_t
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mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
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uint32_t opc1, uint32_t opc2)
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{
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return (isRead << 0) |
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(crm << 1) |
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(rt << 5) |
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(crn << 10) |
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(opc1 << 14) |
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(opc2 << 17);
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}
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static inline void
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mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
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uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
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{
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isRead = (iss >> 0) & 0x1;
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crm = (iss >> 1) & 0xF;
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rt = (IntRegIndex) ((iss >> 5) & 0xF);
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crn = (iss >> 10) & 0xF;
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opc1 = (iss >> 14) & 0x7;
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opc2 = (iss >> 17) & 0x7;
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}
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static inline uint32_t
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mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
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uint32_t opc1)
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{
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return (isRead << 0) |
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(crm << 1) |
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(rt << 5) |
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(rt2 << 10) |
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(opc1 << 16);
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}
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static inline uint32_t
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msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
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uint32_t crm, uint32_t op2, IntRegIndex rt)
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{
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return isRead |
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(crm << 1) |
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(rt << 5) |
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(crn << 10) |
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(op1 << 14) |
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(op2 << 17) |
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(op0 << 20);
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}
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bool
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mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
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HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
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bool
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mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
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HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
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bool
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mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
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HCR hcr, uint32_t iss);
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bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
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CPACR cpacr);
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bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr,
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HCR hcr, bool * isVfpNeon);
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bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
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ExceptionLevel el, bool * isVfpNeon);
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bool
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vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr,
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uint32_t &iss, bool &trap, ThreadContext *tc,
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FPEXC fpexc = (1<<30), bool isSIMD = false);
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static inline bool
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vfpNeon64Enabled(CPACR cpacr, ExceptionLevel el)
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{
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if ((el == EL0 && cpacr.fpen != 0x3) ||
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(el == EL1 && !(cpacr.fpen & 0x1)))
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return false;
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return true;
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}
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bool SPAlignmentCheckEnabled(ThreadContext* tc);
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uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
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void skipFunction(ThreadContext *tc);
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inline void
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advancePC(PCState &pc, const StaticInstPtr inst)
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{
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inst->advancePC(pc);
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}
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Addr truncPage(Addr addr);
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Addr roundPage(Addr addr);
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inline uint64_t
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getExecutingAsid(ThreadContext *tc)
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{
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return tc->readMiscReg(MISCREG_CONTEXTIDR);
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}
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// Decodes the register index to access based on the fields used in a MSR
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// or MRS instruction
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bool
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decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
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CPSR cpsr, SCR scr, NSACR nsacr,
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bool checkSecurity = true);
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// This wrapper function is used to turn the register index into a source
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// parameter for the instruction. See Operands.isa
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static inline int
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decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
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{
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int regIdx;
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bool isIntReg;
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bool validReg;
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validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
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return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
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}
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/**
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* Returns the n. of PA bits corresponding to the specified encoding.
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*/
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int decodePhysAddrRange64(uint8_t pa_enc);
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/**
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* Returns the encoding corresponding to the specified n. of PA bits.
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*/
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uint8_t encodePhysAddrRange64(int pa_size);
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}
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#endif
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