Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
739 lines
20 KiB
C++
739 lines
20 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_TYPES_HH__
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#define __ARCH_ARM_TYPES_HH__
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#include "arch/generic/types.hh"
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#include "base/bitunion.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "debug/Decoder.hh"
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namespace ArmISA
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{
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typedef uint32_t MachInst;
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BitUnion8(ITSTATE)
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/* Note that the split (cond, mask) below is not as in ARM ARM.
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* But it is more convenient for simulation. The condition
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* is always the concatenation of the top 3 bits and the next bit,
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* which applies when one of the bottom 4 bits is set.
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* Refer to predecoder.cc for the use case.
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*/
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Bitfield<7, 4> cond;
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Bitfield<3, 0> mask;
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// Bitfields for moving to/from CPSR
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Bitfield<7, 2> top6;
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Bitfield<1, 0> bottom2;
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EndBitUnion(ITSTATE)
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BitUnion64(ExtMachInst)
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// ITSTATE bits
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Bitfield<55, 48> itstate;
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Bitfield<55, 52> itstateCond;
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Bitfield<51, 48> itstateMask;
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// FPSCR fields
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Bitfield<41, 40> fpscrStride;
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Bitfield<39, 37> fpscrLen;
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// Bitfields to select mode.
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Bitfield<36> thumb;
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Bitfield<35> bigThumb;
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Bitfield<34> aarch64;
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// Made up bitfields that make life easier.
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Bitfield<33> sevenAndFour;
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Bitfield<32> isMisc;
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uint32_t instBits;
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// All the different types of opcode fields.
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Bitfield<27, 25> encoding;
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Bitfield<25> useImm;
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Bitfield<24, 21> opcode;
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Bitfield<24, 20> mediaOpcode;
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Bitfield<24> opcode24;
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Bitfield<24, 23> opcode24_23;
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Bitfield<23, 20> opcode23_20;
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Bitfield<23, 21> opcode23_21;
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Bitfield<20> opcode20;
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Bitfield<22> opcode22;
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Bitfield<19, 16> opcode19_16;
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Bitfield<19> opcode19;
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Bitfield<18> opcode18;
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Bitfield<15, 12> opcode15_12;
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Bitfield<15> opcode15;
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Bitfield<7, 4> miscOpcode;
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Bitfield<7,5> opc2;
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Bitfield<7> opcode7;
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Bitfield<6> opcode6;
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Bitfield<4> opcode4;
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Bitfield<31, 28> condCode;
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Bitfield<20> sField;
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Bitfield<19, 16> rn;
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Bitfield<15, 12> rd;
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Bitfield<15, 12> rt;
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Bitfield<11, 7> shiftSize;
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Bitfield<6, 5> shift;
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Bitfield<3, 0> rm;
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Bitfield<11, 8> rs;
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SubBitUnion(puswl, 24, 20)
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Bitfield<24> prepost;
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Bitfield<23> up;
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Bitfield<22> psruser;
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Bitfield<21> writeback;
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Bitfield<20> loadOp;
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EndSubBitUnion(puswl)
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Bitfield<24, 20> pubwl;
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Bitfield<7, 0> imm;
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Bitfield<11, 8> rotate;
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Bitfield<11, 0> immed11_0;
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Bitfield<7, 0> immed7_0;
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Bitfield<11, 8> immedHi11_8;
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Bitfield<3, 0> immedLo3_0;
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Bitfield<15, 0> regList;
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Bitfield<23, 0> offset;
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Bitfield<23, 0> immed23_0;
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Bitfield<11, 8> cpNum;
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Bitfield<18, 16> fn;
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Bitfield<14, 12> fd;
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Bitfield<3> fpRegImm;
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Bitfield<3, 0> fm;
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Bitfield<2, 0> fpImm;
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Bitfield<24, 20> punwl;
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Bitfield<15, 8> m5Func;
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// 16 bit thumb bitfields
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Bitfield<15, 13> topcode15_13;
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Bitfield<13, 11> topcode13_11;
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Bitfield<12, 11> topcode12_11;
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Bitfield<12, 10> topcode12_10;
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Bitfield<11, 9> topcode11_9;
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Bitfield<11, 8> topcode11_8;
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Bitfield<10, 9> topcode10_9;
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Bitfield<10, 8> topcode10_8;
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Bitfield<9, 6> topcode9_6;
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Bitfield<7> topcode7;
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Bitfield<7, 6> topcode7_6;
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Bitfield<7, 5> topcode7_5;
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Bitfield<7, 4> topcode7_4;
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Bitfield<3, 0> topcode3_0;
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// 32 bit thumb bitfields
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Bitfield<28, 27> htopcode12_11;
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Bitfield<26, 25> htopcode10_9;
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Bitfield<25> htopcode9;
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Bitfield<25, 24> htopcode9_8;
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Bitfield<25, 21> htopcode9_5;
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Bitfield<25, 20> htopcode9_4;
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Bitfield<24> htopcode8;
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Bitfield<24, 23> htopcode8_7;
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Bitfield<24, 22> htopcode8_6;
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Bitfield<24, 21> htopcode8_5;
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Bitfield<23> htopcode7;
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Bitfield<23, 21> htopcode7_5;
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Bitfield<22> htopcode6;
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Bitfield<22, 21> htopcode6_5;
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Bitfield<21, 20> htopcode5_4;
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Bitfield<20> htopcode4;
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Bitfield<19, 16> htrn;
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Bitfield<20> hts;
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Bitfield<15> ltopcode15;
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Bitfield<11, 8> ltopcode11_8;
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Bitfield<7, 6> ltopcode7_6;
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Bitfield<7, 4> ltopcode7_4;
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Bitfield<4> ltopcode4;
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Bitfield<11, 8> ltrd;
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Bitfield<11, 8> ltcoproc;
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EndBitUnion(ExtMachInst)
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class PCState : public GenericISA::UPCState<MachInst>
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{
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protected:
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typedef GenericISA::UPCState<MachInst> Base;
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enum FlagBits {
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ThumbBit = (1 << 0),
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JazelleBit = (1 << 1),
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AArch64Bit = (1 << 2)
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};
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uint8_t flags;
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uint8_t nextFlags;
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uint8_t _itstate;
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uint8_t _nextItstate;
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uint8_t _size;
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public:
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PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)
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{}
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void
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set(Addr val)
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{
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Base::set(val);
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npc(val + (thumb() ? 2 : 4));
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}
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PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)
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{ set(val); }
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bool
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thumb() const
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{
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return flags & ThumbBit;
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}
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void
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thumb(bool val)
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{
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if (val)
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flags |= ThumbBit;
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else
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flags &= ~ThumbBit;
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}
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bool
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nextThumb() const
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{
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return nextFlags & ThumbBit;
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}
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void
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nextThumb(bool val)
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{
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if (val)
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nextFlags |= ThumbBit;
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else
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nextFlags &= ~ThumbBit;
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}
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void size(uint8_t s) { _size = s; }
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uint8_t size() const { return _size; }
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bool
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branching() const
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{
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return ((this->pc() + this->size()) != this->npc());
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}
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bool
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jazelle() const
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{
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return flags & JazelleBit;
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}
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void
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jazelle(bool val)
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{
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if (val)
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flags |= JazelleBit;
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else
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flags &= ~JazelleBit;
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}
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bool
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nextJazelle() const
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{
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return nextFlags & JazelleBit;
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}
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void
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nextJazelle(bool val)
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{
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if (val)
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nextFlags |= JazelleBit;
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else
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nextFlags &= ~JazelleBit;
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}
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bool
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aarch64() const
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{
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return flags & AArch64Bit;
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}
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void
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aarch64(bool val)
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{
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if (val)
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flags |= AArch64Bit;
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else
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flags &= ~AArch64Bit;
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}
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bool
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nextAArch64() const
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{
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return nextFlags & AArch64Bit;
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}
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void
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nextAArch64(bool val)
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{
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if (val)
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nextFlags |= AArch64Bit;
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else
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nextFlags &= ~AArch64Bit;
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}
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uint8_t
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itstate() const
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{
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return _itstate;
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}
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void
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itstate(uint8_t value)
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{
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_itstate = value;
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}
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uint8_t
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nextItstate() const
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{
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return _nextItstate;
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}
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void
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nextItstate(uint8_t value)
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{
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_nextItstate = value;
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}
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void
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advance()
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{
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Base::advance();
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flags = nextFlags;
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npc(pc() + (thumb() ? 2 : 4));
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if (_nextItstate) {
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_itstate = _nextItstate;
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_nextItstate = 0;
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} else if (_itstate) {
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ITSTATE it = _itstate;
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uint8_t cond_mask = it.mask;
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uint8_t thumb_cond = it.cond;
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DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
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thumb_cond, cond_mask);
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cond_mask <<= 1;
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uint8_t new_bit = bits(cond_mask, 4);
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cond_mask &= mask(4);
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if (cond_mask == 0)
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thumb_cond = 0;
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else
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replaceBits(thumb_cond, 0, new_bit);
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DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
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thumb_cond, cond_mask);
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it.mask = cond_mask;
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it.cond = thumb_cond;
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_itstate = it;
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}
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}
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void
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uEnd()
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{
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advance();
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upc(0);
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nupc(1);
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}
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Addr
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instPC() const
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{
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return pc() + (thumb() ? 4 : 8);
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}
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void
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instNPC(Addr val)
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{
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// @todo: review this when AArch32/64 interprocessing is
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// supported
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if (aarch64())
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npc(val); // AArch64 doesn't force PC alignment, a PC
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// Alignment Fault can be raised instead
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else
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npc(val &~ mask(nextThumb() ? 1 : 2));
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}
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Addr
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instNPC() const
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{
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return npc();
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}
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|
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// Perform an interworking branch.
|
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void
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instIWNPC(Addr val)
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{
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bool thumbEE = (thumb() && jazelle());
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Addr newPC = val;
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if (thumbEE) {
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if (bits(newPC, 0)) {
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newPC = newPC & ~mask(1);
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} // else we have a bad interworking address; do not call
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// panic() since the instruction could be executed
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// speculatively
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} else {
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if (bits(newPC, 0)) {
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nextThumb(true);
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newPC = newPC & ~mask(1);
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} else if (!bits(newPC, 1)) {
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nextThumb(false);
|
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} else {
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// This state is UNPREDICTABLE in the ARM architecture
|
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// The easy thing to do is just mask off the bit and
|
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// stay in the current mode, so we'll do that.
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newPC &= ~mask(2);
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}
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}
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npc(newPC);
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}
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|
|
// Perform an interworking branch in ARM mode, a regular branch
|
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// otherwise.
|
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void
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|
instAIWNPC(Addr val)
|
|
{
|
|
if (!thumb() && !jazelle())
|
|
instIWNPC(val);
|
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else
|
|
instNPC(val);
|
|
}
|
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|
|
bool
|
|
operator == (const PCState &opc) const
|
|
{
|
|
return Base::operator == (opc) &&
|
|
flags == opc.flags && nextFlags == opc.nextFlags &&
|
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_itstate == opc._itstate && _nextItstate == opc._nextItstate;
|
|
}
|
|
|
|
bool
|
|
operator != (const PCState &opc) const
|
|
{
|
|
return !(*this == opc);
|
|
}
|
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|
|
void
|
|
serialize(std::ostream &os)
|
|
{
|
|
Base::serialize(os);
|
|
SERIALIZE_SCALAR(flags);
|
|
SERIALIZE_SCALAR(_size);
|
|
SERIALIZE_SCALAR(nextFlags);
|
|
SERIALIZE_SCALAR(_itstate);
|
|
SERIALIZE_SCALAR(_nextItstate);
|
|
}
|
|
|
|
void
|
|
unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
Base::unserialize(cp, section);
|
|
UNSERIALIZE_SCALAR(flags);
|
|
UNSERIALIZE_SCALAR(_size);
|
|
UNSERIALIZE_SCALAR(nextFlags);
|
|
UNSERIALIZE_SCALAR(_itstate);
|
|
UNSERIALIZE_SCALAR(_nextItstate);
|
|
}
|
|
};
|
|
|
|
// Shift types for ARM instructions
|
|
enum ArmShiftType {
|
|
LSL = 0,
|
|
LSR,
|
|
ASR,
|
|
ROR
|
|
};
|
|
|
|
// Extension types for ARM instructions
|
|
enum ArmExtendType {
|
|
UXTB = 0,
|
|
UXTH = 1,
|
|
UXTW = 2,
|
|
UXTX = 3,
|
|
SXTB = 4,
|
|
SXTH = 5,
|
|
SXTW = 6,
|
|
SXTX = 7
|
|
};
|
|
|
|
typedef uint64_t LargestRead;
|
|
// Need to use 64 bits to make sure that read requests get handled properly
|
|
|
|
typedef int RegContextParam;
|
|
typedef int RegContextVal;
|
|
|
|
//used in FP convert & round function
|
|
enum ConvertType{
|
|
SINGLE_TO_DOUBLE,
|
|
SINGLE_TO_WORD,
|
|
SINGLE_TO_LONG,
|
|
|
|
DOUBLE_TO_SINGLE,
|
|
DOUBLE_TO_WORD,
|
|
DOUBLE_TO_LONG,
|
|
|
|
LONG_TO_SINGLE,
|
|
LONG_TO_DOUBLE,
|
|
LONG_TO_WORD,
|
|
LONG_TO_PS,
|
|
|
|
WORD_TO_SINGLE,
|
|
WORD_TO_DOUBLE,
|
|
WORD_TO_LONG,
|
|
WORD_TO_PS,
|
|
|
|
PL_TO_SINGLE,
|
|
PU_TO_SINGLE
|
|
};
|
|
|
|
//used in FP convert & round function
|
|
enum RoundMode{
|
|
RND_ZERO,
|
|
RND_DOWN,
|
|
RND_UP,
|
|
RND_NEAREST
|
|
};
|
|
|
|
enum ExceptionLevel {
|
|
EL0 = 0,
|
|
EL1,
|
|
EL2,
|
|
EL3
|
|
};
|
|
|
|
enum OperatingMode {
|
|
MODE_EL0T = 0x0,
|
|
MODE_EL1T = 0x4,
|
|
MODE_EL1H = 0x5,
|
|
MODE_EL2T = 0x8,
|
|
MODE_EL2H = 0x9,
|
|
MODE_EL3T = 0xC,
|
|
MODE_EL3H = 0xD,
|
|
MODE_USER = 16,
|
|
MODE_FIQ = 17,
|
|
MODE_IRQ = 18,
|
|
MODE_SVC = 19,
|
|
MODE_MON = 22,
|
|
MODE_ABORT = 23,
|
|
MODE_HYP = 26,
|
|
MODE_UNDEFINED = 27,
|
|
MODE_SYSTEM = 31,
|
|
MODE_MAXMODE = MODE_SYSTEM
|
|
};
|
|
|
|
enum ExceptionClass {
|
|
EC_INVALID = -1,
|
|
EC_UNKNOWN = 0x0,
|
|
EC_TRAPPED_WFI_WFE = 0x1,
|
|
EC_TRAPPED_CP15_MCR_MRC = 0x3,
|
|
EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
|
|
EC_TRAPPED_CP14_MCR_MRC = 0x5,
|
|
EC_TRAPPED_CP14_LDC_STC = 0x6,
|
|
EC_TRAPPED_HCPTR = 0x7,
|
|
EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
|
|
EC_TRAPPED_CP10_MRC_VMRS = 0x8,
|
|
EC_TRAPPED_BXJ = 0xA,
|
|
EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
|
|
EC_ILLEGAL_INST = 0xE,
|
|
EC_SVC_TO_HYP = 0x11,
|
|
EC_SVC = 0x11, // AArch64 alias
|
|
EC_HVC = 0x12,
|
|
EC_SMC_TO_HYP = 0x13,
|
|
EC_SMC = 0x13, // AArch64 alias
|
|
EC_SVC_64 = 0x15,
|
|
EC_HVC_64 = 0x16,
|
|
EC_SMC_64 = 0x17,
|
|
EC_TRAPPED_MSR_MRS_64 = 0x18,
|
|
EC_PREFETCH_ABORT_TO_HYP = 0x20,
|
|
EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
|
|
EC_PREFETCH_ABORT_FROM_HYP = 0x21,
|
|
EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
|
|
EC_PC_ALIGNMENT = 0x22,
|
|
EC_DATA_ABORT_TO_HYP = 0x24,
|
|
EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
|
|
EC_DATA_ABORT_FROM_HYP = 0x25,
|
|
EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
|
|
EC_STACK_PTR_ALIGNMENT = 0x26,
|
|
EC_FP_EXCEPTION = 0x28,
|
|
EC_FP_EXCEPTION_64 = 0x2C,
|
|
EC_SERROR = 0x2F
|
|
};
|
|
|
|
BitUnion8(OperatingMode64)
|
|
Bitfield<0> spX;
|
|
Bitfield<3, 2> el;
|
|
Bitfield<4> width;
|
|
EndBitUnion(OperatingMode64)
|
|
|
|
static bool inline
|
|
opModeIs64(OperatingMode mode)
|
|
{
|
|
return ((OperatingMode64)(uint8_t)mode).width == 0;
|
|
}
|
|
|
|
static bool inline
|
|
opModeIsH(OperatingMode mode)
|
|
{
|
|
return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
|
|
}
|
|
|
|
static bool inline
|
|
opModeIsT(OperatingMode mode)
|
|
{
|
|
return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
|
|
mode == MODE_EL3T);
|
|
}
|
|
|
|
static ExceptionLevel inline
|
|
opModeToEL(OperatingMode mode)
|
|
{
|
|
bool aarch32 = ((mode >> 4) & 1) ? true : false;
|
|
if (aarch32) {
|
|
switch (mode) {
|
|
case MODE_USER:
|
|
return EL0;
|
|
case MODE_FIQ:
|
|
case MODE_IRQ:
|
|
case MODE_SVC:
|
|
case MODE_ABORT:
|
|
case MODE_UNDEFINED:
|
|
case MODE_SYSTEM:
|
|
return EL1;
|
|
case MODE_HYP:
|
|
return EL2;
|
|
case MODE_MON:
|
|
return EL3;
|
|
default:
|
|
panic("Invalid operating mode: %d", mode);
|
|
break;
|
|
}
|
|
} else {
|
|
// aarch64
|
|
return (ExceptionLevel) ((mode >> 2) & 3);
|
|
}
|
|
}
|
|
|
|
static inline bool
|
|
badMode(OperatingMode mode)
|
|
{
|
|
switch (mode) {
|
|
case MODE_EL0T:
|
|
case MODE_EL1T:
|
|
case MODE_EL1H:
|
|
case MODE_EL2T:
|
|
case MODE_EL2H:
|
|
case MODE_EL3T:
|
|
case MODE_EL3H:
|
|
case MODE_USER:
|
|
case MODE_FIQ:
|
|
case MODE_IRQ:
|
|
case MODE_SVC:
|
|
case MODE_MON:
|
|
case MODE_ABORT:
|
|
case MODE_HYP:
|
|
case MODE_UNDEFINED:
|
|
case MODE_SYSTEM:
|
|
return false;
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
|
|
static inline bool
|
|
badMode32(OperatingMode mode)
|
|
{
|
|
switch (mode) {
|
|
case MODE_USER:
|
|
case MODE_FIQ:
|
|
case MODE_IRQ:
|
|
case MODE_SVC:
|
|
case MODE_MON:
|
|
case MODE_ABORT:
|
|
case MODE_HYP:
|
|
case MODE_UNDEFINED:
|
|
case MODE_SYSTEM:
|
|
return false;
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
} // namespace ArmISA
|
|
|
|
__hash_namespace_begin
|
|
template<>
|
|
struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
|
|
size_t operator()(const ArmISA::ExtMachInst &emi) const {
|
|
return hash<uint32_t>::operator()((uint32_t)emi);
|
|
};
|
|
};
|
|
__hash_namespace_end
|
|
|
|
#endif
|