Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
616 lines
19 KiB
C++
616 lines
19 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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// Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Load/store microops
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//
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def template MicroMemDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, bool _up,
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uint8_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template MicroMemConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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bool _up,
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uint8_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _up, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Neon load/store microops
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//
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def template MicroNeonMemDeclare {{
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template <class Element>
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst, RegIndex _dest,
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RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
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: %(base_class)s("%(mnemonic)s", machInst,
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%(op_class)s, _dest, _ura, _imm)
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{
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memAccessFlags |= extraMemFlags;
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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////////////////////////////////////////////////////////////////////
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//
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// PC = Integer(ura)
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// CPSR = Integer(urb)
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//
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def template MicroSetPCCPSRDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _ura,
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IntRegIndex _urb,
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IntRegIndex _urc);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroSetPCCPSRConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _ura,
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IntRegIndex _urb,
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IntRegIndex _urc)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _urc)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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flags[IsCondControl] = true;
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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} else {
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flags[IsUncondControl] = true;
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}
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Integer = Integer op Integer microops
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//
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def template MicroIntDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, RegIndex _urc);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroIntConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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RegIndex _urc)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _urc)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MicroNeonMemExecDeclare {{
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template
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Fault %(class_name)s<%(targs)s>::execute(
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%(CPU_exec_context)s *, Trace::InstRecord *) const;
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template
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Fault %(class_name)s<%(targs)s>::initiateAcc(
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%(CPU_exec_context)s *, Trace::InstRecord *) const;
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template
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Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
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%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template MicroNeonExecDeclare {{
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template
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Fault %(class_name)s<%(targs)s>::execute(
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%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Neon (de)interlacing microops
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//
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def template MicroNeonMixDeclare {{
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template <class Element>
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
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uint8_t _step) :
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%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _step)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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%(BasicExecDeclare)s
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};
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}};
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def template MicroNeonMixExecute {{
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template <class Element>
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Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t resTemp = 0;
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resTemp = resTemp;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Neon (un)packing microops using a particular lane
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//
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def template MicroNeonMixLaneDeclare {{
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template <class Element>
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
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uint8_t _step, unsigned _lane) :
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%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _step, _lane)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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%(BasicExecDeclare)s
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};
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Integer = Integer
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//
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def template MicroIntMovDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroIntMovConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Integer = Integer op Immediate microops
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//
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def template MicroIntImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb,
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int32_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroIntImmConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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int32_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template MicroIntImmXConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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int32_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _imm)
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{
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%(constructor)s;
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}
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}};
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def template MicroIntRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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int32_t _shiftAmt, ArmShiftType _shiftType);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroIntXERegConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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ArmExtendType _type, uint32_t _shiftAmt)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _urc, _type, _shiftAmt)
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{
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%(constructor)s;
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}
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}};
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def template MicroIntXERegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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ArmExtendType _type, uint32_t _shiftAmt);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroIntRegConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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int32_t _shiftAmt, ArmShiftType _shiftType)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _urc, _shiftAmt, _shiftType)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Macro Memory-format instructions
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//
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def template MacroMemDeclare {{
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/**
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* Static instructions class for a store multiple instruction
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
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bool index, bool up, bool user, bool writeback, bool load,
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uint32_t reglist);
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%(BasicExecPanic)s
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};
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}};
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def template MacroMemConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
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bool index, bool up, bool user, bool writeback, bool load,
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uint32_t reglist)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
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index, up, user, writeback, load, reglist)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template BigFpMemImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
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%(BasicExecPanic)s
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};
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}};
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def template BigFpMemImmConstructor {{
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%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
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: %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm)
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{
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%(constructor)s;
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}
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}};
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def template BigFpMemRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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bool load, IntRegIndex dest, IntRegIndex base,
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IntRegIndex offset, ArmExtendType type, int64_t imm);
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%(BasicExecPanic)s
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};
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}};
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def template BigFpMemRegConstructor {{
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%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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bool load, IntRegIndex dest, IntRegIndex base,
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IntRegIndex offset, ArmExtendType type, int64_t imm)
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: %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base,
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offset, type, imm)
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{
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%(constructor)s;
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}
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}};
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def template BigFpMemLitDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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IntRegIndex dest, int64_t imm);
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%(BasicExecPanic)s
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};
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}};
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def template BigFpMemLitConstructor {{
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%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
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IntRegIndex dest, int64_t imm)
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: %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm)
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{
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%(constructor)s;
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}
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}};
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def template PairMemDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
|
|
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
|
|
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
|
|
bool exclusive, bool acrel, uint32_t imm,
|
|
AddrMode mode, IntRegIndex rn, IntRegIndex rt,
|
|
IntRegIndex rt2);
|
|
%(BasicExecPanic)s
|
|
};
|
|
}};
|
|
|
|
def template PairMemConstructor {{
|
|
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
|
|
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
|
|
bool exclusive, bool acrel, uint32_t imm, AddrMode mode,
|
|
IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2)
|
|
: %(base_class)s(mnemonic, machInst, %(op_class)s, size,
|
|
fp, load, noAlloc, signExt, exclusive, acrel,
|
|
imm, mode, rn, rt, rt2)
|
|
{
|
|
%(constructor)s;
|
|
}
|
|
}};
|
|
|
|
def template VMemMultDeclare {{
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
// Constructor
|
|
%(class_name)s(ExtMachInst machInst, unsigned width,
|
|
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
|
|
uint32_t size, uint32_t align, RegIndex rm);
|
|
%(BasicExecPanic)s
|
|
};
|
|
}};
|
|
|
|
def template VMemMultConstructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
|
|
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
|
|
uint32_t size, uint32_t align, RegIndex rm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
|
|
rn, vd, regs, inc, size, align, rm)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|
|
def template VMemSingleDeclare {{
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
// Constructor
|
|
%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
|
|
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
|
|
uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
|
|
%(BasicExecPanic)s
|
|
};
|
|
}};
|
|
|
|
def template VMemSingleConstructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
|
|
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
|
|
uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
|
|
rn, vd, regs, inc, size, align, rm, lane)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|
|
def template MacroVFPMemDeclare {{
|
|
/**
|
|
* Static instructions class for a store multiple instruction
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
// Constructor
|
|
%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
|
|
RegIndex vd, bool single, bool up, bool writeback,
|
|
bool load, uint32_t offset);
|
|
%(BasicExecPanic)s
|
|
};
|
|
}};
|
|
|
|
def template MacroVFPMemConstructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
|
|
RegIndex vd, bool single, bool up, bool writeback, bool load,
|
|
uint32_t offset)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
|
|
vd, single, up, writeback, load, offset)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
|
|
}};
|