0acd2a96e5
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
247 lines
8 KiB
C++
247 lines
8 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def template BranchImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, int32_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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def template BranchImmConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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int32_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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flags[IsCondControl] = true;
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} else {
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flags[IsUncondControl] = true;
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}
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}
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}};
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def template BranchImmCondDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, int32_t _imm,
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ConditionCode _condCode);
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%(BasicExecDeclare)s
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ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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};
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}};
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def template BranchImmCondConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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int32_t _imm,
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ConditionCode _condCode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_imm, _condCode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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flags[IsCondControl] = true;
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} else {
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flags[IsUncondControl] = true;
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}
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}
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}};
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def template BranchRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
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%(BasicExecDeclare)s
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};
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}};
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def template BranchRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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flags[IsCondControl] = true;
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} else {
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flags[IsUncondControl] = true;
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}
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if (%(is_ras_pop)s)
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flags[IsReturn] = true;
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}
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}};
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def template BranchRegCondDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
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ConditionCode _condCode);
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%(BasicExecDeclare)s
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};
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}};
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def template BranchRegCondConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1,
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ConditionCode _condCode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_op1, _condCode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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flags[IsCondControl] = true;
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} else {
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flags[IsUncondControl] = true;
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}
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if (%(is_ras_pop)s)
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flags[IsReturn] = true;
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}
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}};
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def template BranchRegRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1, IntRegIndex _op2);
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%(BasicExecDeclare)s
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};
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}};
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def template BranchTableDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1, IntRegIndex _op2);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template BranchRegRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1,
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IntRegIndex _op2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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flags[IsCondControl] = true;
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} else {
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flags[IsUncondControl] = true;
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}
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}
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}};
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def template BranchImmRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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int32_t imm, IntRegIndex _op1);
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%(BasicExecDeclare)s
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};
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}};
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// Only used by CBNZ, CBZ which is conditional based on
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// a register value even though the instruction is always unconditional.
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def template BranchImmRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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int32_t _imm,
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IntRegIndex _op1)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
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{
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%(constructor)s;
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flags[IsCondControl] = true;
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}
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}};
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def template BranchTarget {{
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ArmISA::PCState
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%(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
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{
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%(op_decl)s;
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%(op_rd)s;
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ArmISA::PCState pcs = branchPC;
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%(brTgtCode)s
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pcs.advance();
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return pcs;
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}
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}};
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