612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
453 lines
18 KiB
C++
453 lines
18 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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def operand_types {{
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'sb' : 'int8_t',
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'ub' : 'uint8_t',
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'sh' : 'int16_t',
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'uh' : 'uint16_t',
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'sw' : 'int32_t',
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'uw' : 'uint32_t',
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'ud' : 'uint64_t',
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'tud' : 'Twin64_t',
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'sf' : 'float',
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'df' : 'double'
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}};
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let {{
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maybePCRead = '''
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((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
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'''
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maybeAlignedPCRead = '''
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((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
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xc->%(func)s(this, %(op_idx)s))
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'''
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maybePCWrite = '''
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((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeIWPCWrite = '''
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((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeAIWPCWrite = '''
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if (%(reg_idx)s == PCReg) {
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bool thumb = THUMB;
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if (thumb) {
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setNextPC(xc, %(final_val)s);
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} else {
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setIWNextPC(xc, %(final_val)s);
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}
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} else {
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xc->%(func)s(this, %(op_idx)s, %(final_val)s);
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}
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'''
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aarch64Read = '''
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((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
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'''
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aarch64Write = '''
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xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
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'''
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aarchX64Read = '''
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((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
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'''
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aarchX64Write = '''
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xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
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'''
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aarchW64Read = '''
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((xc->%(func)s(this, %(op_idx)s)) & mask(32))
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'''
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aarchW64Write = '''
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xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
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'''
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cntrlNsBankedWrite = '''
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xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
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'''
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cntrlNsBankedRead = '''
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xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
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'''
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#PCState operands need to have a sorting index (the number at the end)
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#less than all the integer registers which might update the PC. That way
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#if the flag bits of the pc state are updated and a branch happens through
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#R15, the updates are layered properly and the R15 update isn't lost.
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srtNormal = 5
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srtCpsr = 4
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srtBase = 3
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srtPC = 2
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srtMode = 1
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srtEPC = 0
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def floatReg(idx):
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return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
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def intReg(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybePCWrite)
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def intReg64(idx):
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return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
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aarch64Read, aarch64Write)
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def intRegX64(idx, id = srtNormal):
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return ('IntReg', 'ud', idx, 'IsInteger', id,
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aarchX64Read, aarchX64Write)
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def intRegW64(idx, id = srtNormal):
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return ('IntReg', 'ud', idx, 'IsInteger', id,
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aarchW64Read, aarchW64Write)
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def intRegNPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
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def intRegAPC(idx, id = srtNormal):
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return ('IntReg', 'uw', idx, 'IsInteger', id,
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maybeAlignedPCRead, maybePCWrite)
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def intRegIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeIWPCWrite)
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def intRegAIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeAIWPCWrite)
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def intRegCC(idx):
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return ('IntReg', 'uw', idx, None, srtNormal)
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def cntrlReg(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, None, id)
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def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
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def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
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return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
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def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, None, id)
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def pcStateReg(idx, id):
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return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
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}};
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def operands {{
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#Abstracted integer reg operands
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'Dest': intReg('dest'),
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'Dest64': intReg64('dest'),
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'XDest': intRegX64('dest'),
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'WDest': intRegW64('dest'),
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'IWDest': intRegIWPC('dest'),
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'AIWDest': intRegAIWPC('dest'),
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'Dest2': intReg('dest2'),
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'XDest2': intRegX64('dest2'),
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'FDest2': floatReg('dest2'),
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'Result': intReg('result'),
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'XResult': intRegX64('result'),
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'XBase': intRegX64('base', id = srtBase),
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'Base': intRegAPC('base', id = srtBase),
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'XOffset': intRegX64('offset'),
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'Index': intReg('index'),
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'Shift': intReg('shift'),
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'Op1': intReg('op1'),
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'Op2': intReg('op2'),
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'Op3': intReg('op3'),
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'Op164': intReg64('op1'),
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'Op264': intReg64('op2'),
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'Op364': intReg64('op3'),
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'XOp1': intRegX64('op1'),
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'XOp2': intRegX64('op2'),
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'XOp3': intRegX64('op3'),
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'WOp1': intRegW64('op1'),
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'WOp2': intRegW64('op2'),
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'WOp3': intRegW64('op3'),
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'Reg0': intReg('reg0'),
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'Reg1': intReg('reg1'),
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'Reg2': intReg('reg2'),
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'Reg3': intReg('reg3'),
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#Fixed index integer reg operands
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'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
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'LR': intRegNPC('INTREG_LR'),
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'XLR': intRegX64('INTREG_X30'),
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'R7': intRegNPC('7'),
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# First four arguments are passed in registers
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'R0': intRegNPC('0'),
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'R1': intRegNPC('1'),
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'R2': intRegNPC('2'),
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'R3': intRegNPC('3'),
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'X0': intRegX64('0'),
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'X1': intRegX64('1'),
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'X2': intRegX64('2'),
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'X3': intRegX64('3'),
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#Pseudo integer condition code registers
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'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
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'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
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'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
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'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
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'OptCondCodesNZ': intRegCC(
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'''(condCode == COND_AL || condCode == COND_UC ||
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condCode == COND_CC || condCode == COND_CS ||
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condCode == COND_VS || condCode == COND_VC) ?
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INTREG_ZERO : INTREG_CONDCODES_NZ'''),
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'OptCondCodesC': intRegCC(
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'''(condCode == COND_HI || condCode == COND_LS ||
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condCode == COND_CS || condCode == COND_CC) ?
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INTREG_CONDCODES_C : INTREG_ZERO'''),
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'OptShiftRmCondCodesC': intRegCC(
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'''(condCode == COND_HI || condCode == COND_LS ||
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condCode == COND_CS || condCode == COND_CC ||
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shiftType == ROR) ?
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INTREG_CONDCODES_C : INTREG_ZERO'''),
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'OptCondCodesV': intRegCC(
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'''(condCode == COND_VS || condCode == COND_VC ||
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condCode == COND_GE || condCode == COND_LT ||
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condCode == COND_GT || condCode == COND_LE) ?
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INTREG_CONDCODES_V : INTREG_ZERO'''),
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'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
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#Abstracted floating point reg operands
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'FpDest': floatReg('(dest + 0)'),
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'FpDestP0': floatReg('(dest + 0)'),
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'FpDestP1': floatReg('(dest + 1)'),
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'FpDestP2': floatReg('(dest + 2)'),
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'FpDestP3': floatReg('(dest + 3)'),
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'FpDestP4': floatReg('(dest + 4)'),
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'FpDestP5': floatReg('(dest + 5)'),
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'FpDestP6': floatReg('(dest + 6)'),
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'FpDestP7': floatReg('(dest + 7)'),
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'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
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'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
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'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
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'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
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'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
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'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
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'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
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'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
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'FpDest2': floatReg('(dest2 + 0)'),
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'FpDest2P0': floatReg('(dest2 + 0)'),
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'FpDest2P1': floatReg('(dest2 + 1)'),
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'FpDest2P2': floatReg('(dest2 + 2)'),
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'FpDest2P3': floatReg('(dest2 + 3)'),
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'FpOp1': floatReg('(op1 + 0)'),
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'FpOp1P0': floatReg('(op1 + 0)'),
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'FpOp1P1': floatReg('(op1 + 1)'),
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'FpOp1P2': floatReg('(op1 + 2)'),
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'FpOp1P3': floatReg('(op1 + 3)'),
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'FpOp1P4': floatReg('(op1 + 4)'),
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'FpOp1P5': floatReg('(op1 + 5)'),
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'FpOp1P6': floatReg('(op1 + 6)'),
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'FpOp1P7': floatReg('(op1 + 7)'),
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'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
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'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
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'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
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'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
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'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
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'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
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'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
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'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
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'FpOp2': floatReg('(op2 + 0)'),
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'FpOp2P0': floatReg('(op2 + 0)'),
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'FpOp2P1': floatReg('(op2 + 1)'),
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'FpOp2P2': floatReg('(op2 + 2)'),
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'FpOp2P3': floatReg('(op2 + 3)'),
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# Create AArch64 unpacked view of the FP registers
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'AA64FpOp1P0': floatReg('((op1 * 4) + 0)'),
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'AA64FpOp1P1': floatReg('((op1 * 4) + 1)'),
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'AA64FpOp1P2': floatReg('((op1 * 4) + 2)'),
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'AA64FpOp1P3': floatReg('((op1 * 4) + 3)'),
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'AA64FpOp2P0': floatReg('((op2 * 4) + 0)'),
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'AA64FpOp2P1': floatReg('((op2 * 4) + 1)'),
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'AA64FpOp2P2': floatReg('((op2 * 4) + 2)'),
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'AA64FpOp2P3': floatReg('((op2 * 4) + 3)'),
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'AA64FpOp3P0': floatReg('((op3 * 4) + 0)'),
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'AA64FpOp3P1': floatReg('((op3 * 4) + 1)'),
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'AA64FpOp3P2': floatReg('((op3 * 4) + 2)'),
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'AA64FpOp3P3': floatReg('((op3 * 4) + 3)'),
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'AA64FpDestP0': floatReg('((dest * 4) + 0)'),
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'AA64FpDestP1': floatReg('((dest * 4) + 1)'),
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'AA64FpDestP2': floatReg('((dest * 4) + 2)'),
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'AA64FpDestP3': floatReg('((dest * 4) + 3)'),
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'AA64FpDest2P0': floatReg('((dest2 * 4) + 0)'),
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'AA64FpDest2P1': floatReg('((dest2 * 4) + 1)'),
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'AA64FpDest2P2': floatReg('((dest2 * 4) + 2)'),
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'AA64FpDest2P3': floatReg('((dest2 * 4) + 3)'),
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'AA64FpOp1P0V0': floatReg('((((op1+0)) * 4) + 0)'),
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'AA64FpOp1P1V0': floatReg('((((op1+0)) * 4) + 1)'),
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'AA64FpOp1P2V0': floatReg('((((op1+0)) * 4) + 2)'),
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'AA64FpOp1P3V0': floatReg('((((op1+0)) * 4) + 3)'),
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'AA64FpOp1P0V1': floatReg('((((op1+1)) * 4) + 0)'),
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'AA64FpOp1P1V1': floatReg('((((op1+1)) * 4) + 1)'),
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'AA64FpOp1P2V1': floatReg('((((op1+1)) * 4) + 2)'),
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'AA64FpOp1P3V1': floatReg('((((op1+1)) * 4) + 3)'),
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'AA64FpOp1P0V2': floatReg('((((op1+2)) * 4) + 0)'),
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'AA64FpOp1P1V2': floatReg('((((op1+2)) * 4) + 1)'),
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'AA64FpOp1P2V2': floatReg('((((op1+2)) * 4) + 2)'),
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'AA64FpOp1P3V2': floatReg('((((op1+2)) * 4) + 3)'),
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'AA64FpOp1P0V3': floatReg('((((op1+3)) * 4) + 0)'),
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'AA64FpOp1P1V3': floatReg('((((op1+3)) * 4) + 1)'),
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'AA64FpOp1P2V3': floatReg('((((op1+3)) * 4) + 2)'),
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'AA64FpOp1P3V3': floatReg('((((op1+3)) * 4) + 3)'),
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'AA64FpOp1P0V0S': floatReg('((((op1+0)%32) * 4) + 0)'),
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'AA64FpOp1P1V0S': floatReg('((((op1+0)%32) * 4) + 1)'),
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'AA64FpOp1P2V0S': floatReg('((((op1+0)%32) * 4) + 2)'),
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'AA64FpOp1P3V0S': floatReg('((((op1+0)%32) * 4) + 3)'),
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'AA64FpOp1P0V1S': floatReg('((((op1+1)%32) * 4) + 0)'),
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'AA64FpOp1P1V1S': floatReg('((((op1+1)%32) * 4) + 1)'),
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'AA64FpOp1P2V1S': floatReg('((((op1+1)%32) * 4) + 2)'),
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'AA64FpOp1P3V1S': floatReg('((((op1+1)%32) * 4) + 3)'),
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'AA64FpOp1P0V2S': floatReg('((((op1+2)%32) * 4) + 0)'),
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'AA64FpOp1P1V2S': floatReg('((((op1+2)%32) * 4) + 1)'),
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'AA64FpOp1P2V2S': floatReg('((((op1+2)%32) * 4) + 2)'),
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'AA64FpOp1P3V2S': floatReg('((((op1+2)%32) * 4) + 3)'),
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'AA64FpOp1P0V3S': floatReg('((((op1+3)%32) * 4) + 0)'),
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'AA64FpOp1P1V3S': floatReg('((((op1+3)%32) * 4) + 1)'),
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'AA64FpOp1P2V3S': floatReg('((((op1+3)%32) * 4) + 2)'),
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'AA64FpOp1P3V3S': floatReg('((((op1+3)%32) * 4) + 3)'),
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|
|
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'AA64FpDestP0V0': floatReg('((((dest+0)) * 4) + 0)'),
|
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'AA64FpDestP1V0': floatReg('((((dest+0)) * 4) + 1)'),
|
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'AA64FpDestP2V0': floatReg('((((dest+0)) * 4) + 2)'),
|
|
'AA64FpDestP3V0': floatReg('((((dest+0)) * 4) + 3)'),
|
|
|
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'AA64FpDestP0V1': floatReg('((((dest+1)) * 4) + 0)'),
|
|
'AA64FpDestP1V1': floatReg('((((dest+1)) * 4) + 1)'),
|
|
'AA64FpDestP2V1': floatReg('((((dest+1)) * 4) + 2)'),
|
|
'AA64FpDestP3V1': floatReg('((((dest+1)) * 4) + 3)'),
|
|
|
|
'AA64FpDestP0V0L': floatReg('((((dest+0)%32) * 4) + 0)'),
|
|
'AA64FpDestP1V0L': floatReg('((((dest+0)%32) * 4) + 1)'),
|
|
'AA64FpDestP2V0L': floatReg('((((dest+0)%32) * 4) + 2)'),
|
|
'AA64FpDestP3V0L': floatReg('((((dest+0)%32) * 4) + 3)'),
|
|
|
|
'AA64FpDestP0V1L': floatReg('((((dest+1)%32) * 4) + 0)'),
|
|
'AA64FpDestP1V1L': floatReg('((((dest+1)%32) * 4) + 1)'),
|
|
'AA64FpDestP2V1L': floatReg('((((dest+1)%32) * 4) + 2)'),
|
|
'AA64FpDestP3V1L': floatReg('((((dest+1)%32) * 4) + 3)'),
|
|
|
|
#Abstracted control reg operands
|
|
'MiscDest': cntrlReg('dest'),
|
|
'MiscOp1': cntrlReg('op1'),
|
|
'MiscNsBankedDest': cntrlNsBankedReg('dest'),
|
|
'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
|
|
'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
|
|
'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
|
|
|
|
#Fixed index control regs
|
|
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
|
|
'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
|
|
'Spsr': cntrlRegNC('MISCREG_SPSR'),
|
|
'Fpsr': cntrlRegNC('MISCREG_FPSR'),
|
|
'Fpsid': cntrlRegNC('MISCREG_FPSID'),
|
|
'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
|
|
'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
|
|
'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
|
|
'Cpacr': cntrlReg('MISCREG_CPACR'),
|
|
'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
|
|
'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
|
|
'Nsacr': cntrlReg('MISCREG_NSACR'),
|
|
'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
|
|
'Hcr': cntrlReg('MISCREG_HCR'),
|
|
'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
|
|
'Hdcr': cntrlReg('MISCREG_HDCR'),
|
|
'Hcptr': cntrlReg('MISCREG_HCPTR'),
|
|
'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
|
|
'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
|
|
'Hstr': cntrlReg('MISCREG_HSTR'),
|
|
'Scr': cntrlReg('MISCREG_SCR'),
|
|
'Scr64': cntrlReg('MISCREG_SCR_EL3'),
|
|
'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
|
|
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
|
|
'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
|
|
'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
|
|
|
|
#Register fields for microops
|
|
'URa' : intReg('ura'),
|
|
'XURa' : intRegX64('ura'),
|
|
'WURa' : intRegW64('ura'),
|
|
'IWRa' : intRegIWPC('ura'),
|
|
'Fa' : floatReg('ura'),
|
|
'FaP1' : floatReg('ura + 1'),
|
|
'URb' : intReg('urb'),
|
|
'XURb' : intRegX64('urb'),
|
|
'URc' : intReg('urc'),
|
|
'XURc' : intRegX64('urc'),
|
|
|
|
#Memory Operand
|
|
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
|
|
|
|
#PCState fields
|
|
'RawPC': pcStateReg('pc', srtPC),
|
|
'PC': pcStateReg('instPC', srtPC),
|
|
'NPC': pcStateReg('instNPC', srtPC),
|
|
'pNPC': pcStateReg('instNPC', srtEPC),
|
|
'IWNPC': pcStateReg('instIWNPC', srtPC),
|
|
'Thumb': pcStateReg('thumb', srtPC),
|
|
'NextThumb': pcStateReg('nextThumb', srtMode),
|
|
'NextJazelle': pcStateReg('nextJazelle', srtMode),
|
|
'NextItState': pcStateReg('nextItstate', srtMode),
|
|
'Itstate': pcStateReg('itstate', srtMode),
|
|
|
|
#Register operands depending on a field in the instruction encoding. These
|
|
#should be avoided since they may not be portable across different
|
|
#encodings of the same instruction.
|
|
'Rd': intReg('RD'),
|
|
'Rm': intReg('RM'),
|
|
'Rs': intReg('RS'),
|
|
'Rn': intReg('RN'),
|
|
'Rt': intReg('RT')
|
|
}};
|