612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
388 lines
15 KiB
C++
388 lines
15 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2011 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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import math
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header_output = ""
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decoder_output = ""
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exec_output = ""
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class StoreInst(LoadStoreInst):
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execBase = 'Store'
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def __init__(self, mnem, post, add, writeback, size=4,
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sign=False, user=False, flavor="normal",
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instFlags = []):
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super(StoreInst, self).__init__()
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self.name = mnem
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self.post = post
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self.add = add
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self.writeback = writeback
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self.size = size
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self.sign = sign
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self.user = user
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self.flavor = flavor
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self.instFlags = instFlags
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if self.add:
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self.op = " +"
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else:
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self.op = " -"
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self.memFlags = ["ArmISA::TLB::MustBeOne"]
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self.codeBlobs = { "postacc_code" : "" }
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def emitHelper(self, base = 'Memory', wbDecl = None):
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global header_output, decoder_output, exec_output
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codeBlobs = self.codeBlobs
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codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
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(newHeader,
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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self.memFlags, self.instFlags,
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base, wbDecl, None, False,
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self.size, self.sign)
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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class SrsInst(LoadStoreInst):
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execBase = 'Store'
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decConstBase = 'Srs'
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def __init__(self, mnem, post, add, writeback):
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super(SrsInst, self).__init__()
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self.name = mnem
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self.post = post
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self.add = add
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self.writeback = writeback
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self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
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def emit(self):
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offset = 0
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if self.post != self.add:
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offset += 4
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if not self.add:
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offset -= 8
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eaCode = "EA = SpMode + %d;" % offset
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wbDiff = -8
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if self.add:
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wbDiff = 8
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accCode = '''
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CPSR cpsr = Cpsr;
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Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
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((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
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'''
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global header_output, decoder_output, exec_output
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codeBlobs = { "ea_code": eaCode,
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"memacc_code": accCode,
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"postacc_code": "" }
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codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
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wbDecl = None
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if self.writeback:
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wbDecl = '''MicroAddiUop(machInst,
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intRegInMode((OperatingMode)regMode, INTREG_SP),
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intRegInMode((OperatingMode)regMode, INTREG_SP),
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%d);''' % wbDiff
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(newHeader,
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
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'SrsOp', wbDecl)
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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class StoreImmInst(StoreInst):
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def __init__(self, *args, **kargs):
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super(StoreImmInst, self).__init__(*args, **kargs)
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self.offset = self.op + " imm"
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if self.add:
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self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
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else:
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self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
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class StoreRegInst(StoreInst):
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def __init__(self, *args, **kargs):
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super(StoreRegInst, self).__init__(*args, **kargs)
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self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
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" shiftType, OptShiftRmCondCodesC)"
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if self.add:
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self.wbDecl = '''
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MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
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'''
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else:
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self.wbDecl = '''
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MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
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'''
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class StoreSingle(StoreInst):
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def __init__(self, *args, **kargs):
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super(StoreSingle, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback,
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self.size, self.sign, self.user)
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# Add memory request flags where necessary
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self.memFlags.append("%d" % int(math.log(self.size, 2)))
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if self.user:
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self.memFlags.append("ArmISA::TLB::UserMode")
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if self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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elif self.flavor != "fp":
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self.memFlags.append("ArmISA::TLB::AllowUnaligned")
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# Disambiguate the class name for different flavors of stores
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address computation
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eaCode = "EA = Base"
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if not self.post:
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eaCode += self.offset
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eaCode += ";"
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if self.flavor == "fp":
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eaCode += vfpEnabledCheckCode
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self.codeBlobs["ea_code"] = eaCode
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# Code that actually handles the access
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if self.flavor == "fp":
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accCode = 'Mem%(suffix)s = cSwap(FpDest_uw, ((CPSR)Cpsr).e);'
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else:
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accCode = \
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'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
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accCode = accCode % \
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{ "suffix" : buildMemSuffix(self.sign, self.size) }
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self.codeBlobs["memacc_code"] = accCode
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# Push it out to the output files
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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wbDecl = None
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if self.writeback:
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wbDecl = self.wbDecl
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self.emitHelper(base, wbDecl)
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def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
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return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
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class StoreImmEx(StoreImmInst, StoreSingle):
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execBase = 'StoreEx'
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decConstBase = 'StoreExImm'
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basePrefix = 'MemoryExImm'
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nameFunc = staticmethod(storeImmClassName)
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def __init__(self, *args, **kargs):
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super(StoreImmEx, self).__init__(*args, **kargs)
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self.codeBlobs["postacc_code"] = "Result = !writeResult;"
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class StoreImm(StoreImmInst, StoreSingle):
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decConstBase = 'LoadStoreImm'
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basePrefix = 'MemoryImm'
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nameFunc = staticmethod(storeImmClassName)
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def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
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return memClassName("STORE_REG", post, add, writeback, size, sign, user)
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class StoreReg(StoreRegInst, StoreSingle):
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decConstBase = 'StoreReg'
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basePrefix = 'MemoryReg'
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nameFunc = staticmethod(storeRegClassName)
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class StoreDouble(StoreInst):
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def __init__(self, *args, **kargs):
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super(StoreDouble, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback)
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# Add memory request flags where necessary
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if self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
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else:
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self.memFlags.append("ArmISA::TLB::AlignWord")
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# Disambiguate the class name for different flavors of stores
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address computation code
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eaCode = "EA = Base"
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if not self.post:
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eaCode += self.offset
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eaCode += ";"
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if self.flavor == "fp":
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eaCode += vfpEnabledCheckCode
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self.codeBlobs["ea_code"] = eaCode
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# Code that actually handles the access
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if self.flavor == "fp":
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accCode = '''
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uint64_t swappedMem = (uint64_t)FpDest_uw |
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((uint64_t)FpDest2_uw << 32);
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Mem_ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
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'''
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else:
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accCode = '''
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CPSR cpsr = Cpsr;
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Mem_ud = (uint64_t)cSwap(Dest_uw, cpsr.e) |
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((uint64_t)cSwap(Dest2_uw, cpsr.e) << 32);
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'''
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self.codeBlobs["memacc_code"] = accCode
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# Push it out to the output files
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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wbDecl = None
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if self.writeback:
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wbDecl = self.wbDecl
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self.emitHelper(base, wbDecl)
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def storeDoubleImmClassName(post, add, writeback):
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return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
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class StoreDoubleImmEx(StoreImmInst, StoreDouble):
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execBase = 'StoreEx'
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decConstBase = 'StoreExDImm'
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basePrefix = 'MemoryExDImm'
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nameFunc = staticmethod(storeDoubleImmClassName)
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def __init__(self, *args, **kargs):
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super(StoreDoubleImmEx, self).__init__(*args, **kargs)
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self.codeBlobs["postacc_code"] = "Result = !writeResult;"
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class StoreDoubleImm(StoreImmInst, StoreDouble):
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decConstBase = 'LoadStoreDImm'
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basePrefix = 'MemoryDImm'
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nameFunc = staticmethod(storeDoubleImmClassName)
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def storeDoubleRegClassName(post, add, writeback):
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return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
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class StoreDoubleReg(StoreRegInst, StoreDouble):
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decConstBase = 'StoreDReg'
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basePrefix = 'MemoryDReg'
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nameFunc = staticmethod(storeDoubleRegClassName)
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def buildStores(mnem, size=4, sign=False, user=False):
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StoreImm(mnem, True, True, True, size, sign, user).emit()
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StoreReg(mnem, True, True, True, size, sign, user).emit()
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StoreImm(mnem, True, False, True, size, sign, user).emit()
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StoreReg(mnem, True, False, True, size, sign, user).emit()
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StoreImm(mnem, False, True, True, size, sign, user).emit()
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StoreReg(mnem, False, True, True, size, sign, user).emit()
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StoreImm(mnem, False, False, True, size, sign, user).emit()
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StoreReg(mnem, False, False, True, size, sign, user).emit()
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StoreImm(mnem, False, True, False, size, sign, user).emit()
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StoreReg(mnem, False, True, False, size, sign, user).emit()
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StoreImm(mnem, False, False, False, size, sign, user).emit()
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StoreReg(mnem, False, False, False, size, sign, user).emit()
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def buildDoubleStores(mnem):
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StoreDoubleImm(mnem, True, True, True).emit()
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StoreDoubleReg(mnem, True, True, True).emit()
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StoreDoubleImm(mnem, True, False, True).emit()
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StoreDoubleReg(mnem, True, False, True).emit()
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StoreDoubleImm(mnem, False, True, True).emit()
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StoreDoubleReg(mnem, False, True, True).emit()
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StoreDoubleImm(mnem, False, False, True).emit()
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StoreDoubleReg(mnem, False, False, True).emit()
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StoreDoubleImm(mnem, False, True, False).emit()
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StoreDoubleReg(mnem, False, True, False).emit()
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StoreDoubleImm(mnem, False, False, False).emit()
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StoreDoubleReg(mnem, False, False, False).emit()
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def buildSrsStores(mnem):
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SrsInst(mnem, True, True, True).emit()
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SrsInst(mnem, True, True, False).emit()
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SrsInst(mnem, True, False, True).emit()
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SrsInst(mnem, True, False, False).emit()
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SrsInst(mnem, False, True, True).emit()
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SrsInst(mnem, False, True, False).emit()
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SrsInst(mnem, False, False, True).emit()
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SrsInst(mnem, False, False, False).emit()
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buildStores("str")
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buildStores("strt", user=True)
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buildStores("strb", size=1)
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buildStores("strbt", size=1, user=True)
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buildStores("strh", size=2)
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buildStores("strht", size=2, user=True)
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buildSrsStores("srs")
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buildDoubleStores("strd")
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StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
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instFlags = ['IsStoreConditional']).emit()
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StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
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instFlags = ['IsStoreConditional']).emit()
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StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
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instFlags = ['IsStoreConditional']).emit()
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StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
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instFlags = ['IsStoreConditional']).emit()
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StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
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StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
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StoreDoubleImm("vstr", False, True, False, flavor="fp").emit()
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StoreDoubleImm("vstr", False, False, False, flavor="fp").emit()
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}};
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