Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
137 lines
5.2 KiB
C++
137 lines
5.2 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// The actual ARM ISA decoder
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// --------------------------
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// The following instructions are specified in the ARM ISA
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// Specification. Decoding closely follows the style specified
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// in the ARM ISA specification document starting with Table B.1 or 3-1
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//
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//
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decode COND_CODE {
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0xF: ArmUnconditional::armUnconditional();
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default: decode ENCODING {
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format DataOp {
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0x0: decode SEVEN_AND_FOUR {
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1: decode MISC_OPCODE {
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0x9: decode PREPOST {
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0: ArmMultAndMultAcc::armMultAndMultAcc();
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1: ArmSyncMem::armSyncMem();
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}
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0xb, 0xd, 0xf: AddrMode3::addrMode3();
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}
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0: decode IS_MISC {
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0: ArmDataProcReg::armDataProcReg();
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1: decode OPCODE_7 {
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0x0: decode MISC_OPCODE {
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0x0: ArmMsrMrs::armMsrMrs();
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// bxj unimplemented, treated as bx
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0x1,0x2: ArmBxClz::armBxClz();
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0x3: decode OPCODE {
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0x9: ArmBlxReg::armBlxReg();
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}
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0x5: ArmSatAddSub::armSatAddSub();
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0x6: ArmERet::armERet();
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0x7: decode OPCODE_22 {
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0: Breakpoint::bkpt();
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1: ArmSmcHyp::armSmcHyp();
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}
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}
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0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
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}
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}
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}
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0x1: decode IS_MISC {
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0: ArmDataProcImm::armDataProcImm();
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1: ArmMisc::armMisc();
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}
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0x2: AddrMode2::addrMode2(True);
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0x3: decode OPCODE_4 {
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0: AddrMode2::addrMode2(False);
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1: decode OPCODE_24_23 {
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0x0: ArmParallelAddSubtract::armParallelAddSubtract();
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0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
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0x2: ArmSignedMultiplies::armSignedMultiplies();
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0x3: decode MEDIA_OPCODE {
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0x1F: decode OPC2 {
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default: ArmMiscMedia::armMiscMedia();
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}
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default: ArmMiscMedia::armMiscMedia();
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}
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}
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}
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0x4: ArmMacroMem::armMacroMem();
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0x5: decode OPCODE_24 {
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0: ArmBBlxImm::armBBlxImm();
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1: ArmBlBlxImm::armBlBlxImm();
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}
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0x6: decode CPNUM {
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0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
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0xf: decode OPCODE_20 {
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0: Mcrr15::Mcrr15();
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1: Mrrc15::Mrrc15();
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}
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}
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0x7: decode OPCODE_24 {
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0: decode OPCODE_4 {
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0: decode CPNUM {
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0xa, 0xb: VfpData::vfpData();
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} // CPNUM
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1: decode CPNUM { // 27-24=1110,4 ==1
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0x1: M5ops::m5ops();
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0xa, 0xb: ShortFpTransfer::shortFpTransfer();
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0xe: McrMrc14::mcrMrc14();
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0xf: McrMrc15::mcrMrc15();
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} // CPNUM (OP4 == 1)
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} //OPCODE_4
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1: Svc::svc();
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} // OPCODE_24
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}
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}
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}
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