612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
370 lines
13 KiB
C++
370 lines
13 KiB
C++
/*
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* Copyright (c) 2010-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
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#define __ARCH_ARM_INSTS_STATICINST_HH__
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#include "arch/arm/faults.hh"
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#include "arch/arm/utility.hh"
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#include "arch/arm/system.hh"
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#include "base/trace.hh"
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#include "cpu/static_inst.hh"
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#include "sim/byteswap.hh"
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#include "sim/full_system.hh"
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namespace ArmISA
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{
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class ArmStaticInst : public StaticInst
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{
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protected:
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bool aarch64;
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uint8_t intWidth;
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int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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bool shift_carry_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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bool shift_carry_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
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ArmShiftType type, uint8_t width) const;
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int64_t extendReg64(uint64_t base, ArmExtendType type,
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uint64_t shiftAmt, uint8_t width) const;
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template<int width>
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static inline bool
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saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
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{
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int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
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if (bits(midRes, width) != bits(midRes, width - 1)) {
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if (midRes > 0)
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res = (LL(1) << (width - 1)) - 1;
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else
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res = -(LL(1) << (width - 1));
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return true;
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} else {
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res = midRes;
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return false;
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}
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}
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static inline bool
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satInt(int32_t &res, int64_t op, int width)
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{
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width--;
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if (op >= (LL(1) << width)) {
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res = (LL(1) << width) - 1;
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return true;
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} else if (op < -(LL(1) << width)) {
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res = -(LL(1) << width);
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return true;
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} else {
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res = op;
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return false;
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}
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}
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template<int width>
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static inline bool
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uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
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{
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int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
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if (midRes >= (LL(1) << width)) {
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res = (LL(1) << width) - 1;
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return true;
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} else if (midRes < 0) {
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res = 0;
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return true;
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} else {
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res = midRes;
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return false;
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}
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}
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static inline bool
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uSatInt(int32_t &res, int64_t op, int width)
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{
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if (op >= (LL(1) << width)) {
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res = (LL(1) << width) - 1;
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return true;
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} else if (op < 0) {
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res = 0;
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return true;
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} else {
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res = op;
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return false;
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}
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}
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// Constructor
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ArmStaticInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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aarch64 = machInst.aarch64;
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if (bits(machInst, 28, 24) == 0x10)
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intWidth = 64; // Force 64-bit width for ADR/ADRP
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else
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intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
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}
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/// Print a register name for disassembly given the unique
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/// dependence tag number (FP or int).
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void printReg(std::ostream &os, int reg) const;
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void printMnemonic(std::ostream &os,
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const std::string &suffix = "",
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bool withPred = true,
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bool withCond64 = false,
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ConditionCode cond64 = COND_UC) const;
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void printTarget(std::ostream &os, Addr target,
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const SymbolTable *symtab) const;
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void printCondition(std::ostream &os, unsigned code,
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bool noImplicit=false) const;
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void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
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const std::string &prefix, const Addr addr,
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const std::string &suffix) const;
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void printShiftOperand(std::ostream &os, IntRegIndex rm,
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bool immShift, uint32_t shiftAmt,
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IntRegIndex rs, ArmShiftType type) const;
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void printExtendOperand(bool firstOperand, std::ostream &os,
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IntRegIndex rm, ArmExtendType type,
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int64_t shiftAmt) const;
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void printDataInst(std::ostream &os, bool withImm) const;
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void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
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IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
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IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
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uint32_t imm) const;
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void
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advancePC(PCState &pcState) const
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{
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pcState.advance();
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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static inline uint32_t
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cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
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uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
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{
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bool privileged = (cpsr.mode != MODE_USER);
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bool haveVirt = ArmSystem::haveVirtualization(tc);
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bool haveSecurity = ArmSystem::haveSecurity(tc);
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bool isSecure = inSecureState(scr, cpsr) || !haveSecurity;
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uint32_t bitMask = 0;
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if (bits(byteMask, 3)) {
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unsigned lowIdx = affectState ? 24 : 27;
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bitMask = bitMask | mask(31, lowIdx);
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}
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if (bits(byteMask, 2)) {
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bitMask = bitMask | mask(19, 16);
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}
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if (bits(byteMask, 1)) {
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unsigned highIdx = affectState ? 15 : 9;
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unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
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? 8 : 9;
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bitMask = bitMask | mask(highIdx, lowIdx);
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}
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if (bits(byteMask, 0)) {
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if (privileged) {
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bitMask |= 1 << 7;
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if ( (!nmfi || !((val >> 6) & 0x1)) &&
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(isSecure || scr.fw || haveVirt) ) {
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bitMask |= 1 << 6;
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}
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// Now check the new mode is allowed
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OperatingMode newMode = (OperatingMode) (val & mask(5));
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OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
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if (!badMode(newMode)) {
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bool validModeChange = true;
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// Check for attempts to enter modes only permitted in
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// Secure state from Non-secure state. These are Monitor
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// mode ('10110'), and FIQ mode ('10001') if the Security
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// Extensions have reserved it.
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if (!isSecure && newMode == MODE_MON)
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validModeChange = false;
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if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
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validModeChange = false;
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// There is no Hyp mode ('11010') in Secure state, so that
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// is UNPREDICTABLE
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if (scr.ns == '0' && newMode == MODE_HYP)
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validModeChange = false;
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// Cannot move into Hyp mode directly from a Non-secure
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// PL1 mode
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if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
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validModeChange = false;
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// Cannot move out of Hyp mode with this function except
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// on an exception return
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if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
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validModeChange = false;
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// Must not change to 64 bit when running in 32 bit mode
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if (!opModeIs64(oldMode) && opModeIs64(newMode))
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validModeChange = false;
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// If we passed all of the above then set the bit mask to
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// copy the mode accross
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if (validModeChange) {
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bitMask = bitMask | mask(5);
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} else {
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warn_once("Illegal change to CPSR mode attempted\n");
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}
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} else {
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warn_once("Ignoring write of bad mode to CPSR.\n");
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}
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}
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if (affectState)
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bitMask = bitMask | (1 << 5);
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}
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return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
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}
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static inline uint32_t
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spsrWriteByInstr(uint32_t spsr, uint32_t val,
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uint8_t byteMask, bool affectState)
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{
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uint32_t bitMask = 0;
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if (bits(byteMask, 3))
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bitMask = bitMask | mask(31, 24);
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if (bits(byteMask, 2))
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bitMask = bitMask | mask(19, 16);
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if (bits(byteMask, 1))
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bitMask = bitMask | mask(15, 8);
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if (bits(byteMask, 0))
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bitMask = bitMask | mask(7, 0);
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return ((spsr & ~bitMask) | (val & bitMask));
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}
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template<class XC>
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static inline Addr
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readPC(XC *xc)
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{
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return xc->pcState().instPC();
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}
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template<class XC>
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static inline void
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setNextPC(XC *xc, Addr val)
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{
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PCState pc = xc->pcState();
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pc.instNPC(val);
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xc->pcState(pc);
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}
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template<class T>
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static inline T
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cSwap(T val, bool big)
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{
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if (big) {
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return gtobe(val);
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} else {
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return gtole(val);
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}
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}
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template<class T, class E>
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static inline T
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cSwap(T val, bool big)
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{
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const unsigned count = sizeof(T) / sizeof(E);
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union {
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T tVal;
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E eVals[count];
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} conv;
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conv.tVal = htog(val);
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if (big) {
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for (unsigned i = 0; i < count; i++) {
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conv.eVals[i] = gtobe(conv.eVals[i]);
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}
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} else {
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for (unsigned i = 0; i < count; i++) {
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conv.eVals[i] = gtole(conv.eVals[i]);
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}
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}
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return gtoh(conv.tVal);
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}
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// Perform an interworking branch.
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template<class XC>
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static inline void
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setIWNextPC(XC *xc, Addr val)
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{
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PCState pc = xc->pcState();
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pc.instIWNPC(val);
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xc->pcState(pc);
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}
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// Perform an interworking branch in ARM mode, a regular branch
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// otherwise.
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template<class XC>
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static inline void
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setAIWNextPC(XC *xc, Addr val)
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{
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PCState pc = xc->pcState();
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pc.instAIWNPC(val);
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xc->pcState(pc);
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}
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inline Fault
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disabledFault() const
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{
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return new UndefinedInstruction(machInst, false, mnemonic, true);
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}
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public:
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virtual void
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annotateFault(ArmFault *fault) {}
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};
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}
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#endif //__ARCH_ARM_INSTS_STATICINST_HH__
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