612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
518 lines
15 KiB
C++
518 lines
15 KiB
C++
/*
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* Copyright (c) 2010-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_MACROMEM_HH__
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#define __ARCH_ARM_MACROMEM_HH__
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#include "arch/arm/insts/pred_inst.hh"
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#include "arch/arm/tlb.hh"
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namespace ArmISA
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{
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static inline unsigned int
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number_of_ones(int32_t val)
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{
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uint32_t ones = 0;
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for (int i = 0; i < 32; i++ )
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{
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if ( val & (1<<i) )
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ones++;
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}
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return ones;
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}
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/**
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* Base class for Memory microops
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*/
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class MicroOp : public PredOp
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{
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protected:
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MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
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: PredOp(mnem, machInst, __opClass)
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{
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}
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public:
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void
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advancePC(PCState &pcState) const
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{
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if (flags[IsLastMicroop]) {
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pcState.uEnd();
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} else if (flags[IsMicroop]) {
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pcState.uAdvance();
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} else {
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pcState.advance();
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}
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}
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};
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class MicroOpX : public ArmStaticInst
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{
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protected:
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MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
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: ArmStaticInst(mnem, machInst, __opClass)
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{}
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public:
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void
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advancePC(PCState &pcState) const
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{
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if (flags[IsLastMicroop]) {
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pcState.uEnd();
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} else if (flags[IsMicroop]) {
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pcState.uAdvance();
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} else {
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pcState.advance();
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}
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}
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};
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/**
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* Microops for Neon loads/stores
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*/
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class MicroNeonMemOp : public MicroOp
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{
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protected:
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RegIndex dest, ura;
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uint32_t imm;
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unsigned memAccessFlags;
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MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _dest, RegIndex _ura, uint32_t _imm)
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: MicroOp(mnem, machInst, __opClass),
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dest(_dest), ura(_ura), imm(_imm),
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memAccessFlags(TLB::MustBeOne)
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{
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}
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};
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/**
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* Microops for Neon load/store (de)interleaving
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*/
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class MicroNeonMixOp : public MicroOp
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{
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protected:
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RegIndex dest, op1;
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uint32_t step;
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MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _dest, RegIndex _op1, uint32_t _step)
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: MicroOp(mnem, machInst, __opClass),
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dest(_dest), op1(_op1), step(_step)
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{
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}
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};
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class MicroNeonMixLaneOp : public MicroNeonMixOp
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{
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protected:
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unsigned lane;
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MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
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OpClass __opClass, RegIndex _dest, RegIndex _op1,
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uint32_t _step, unsigned _lane)
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: MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
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lane(_lane)
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{
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}
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};
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/**
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* Microops for AArch64 NEON load/store (de)interleaving
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*/
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class MicroNeonMixOp64 : public MicroOp
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{
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protected:
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RegIndex dest, op1;
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uint8_t eSize, dataSize, numStructElems, numRegs, step;
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MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _dest, RegIndex _op1, uint8_t _eSize,
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uint8_t _dataSize, uint8_t _numStructElems,
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uint8_t _numRegs, uint8_t _step)
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: MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
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eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
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numRegs(_numRegs), step(_step)
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{
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}
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};
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class MicroNeonMixLaneOp64 : public MicroOp
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{
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protected:
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RegIndex dest, op1;
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uint8_t eSize, dataSize, numStructElems, lane, step;
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bool replicate;
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MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst,
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OpClass __opClass, RegIndex _dest, RegIndex _op1,
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uint8_t _eSize, uint8_t _dataSize,
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uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
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bool _replicate = false)
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: MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
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eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
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lane(_lane), step(_step), replicate(_replicate)
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{
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}
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};
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/**
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* Base classes for microcoded AArch64 NEON memory instructions.
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*/
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class VldMultOp64 : public PredMacroOp
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{
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protected:
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uint8_t eSize, dataSize, numStructElems, numRegs;
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bool wb;
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VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
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uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
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bool wb);
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};
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class VstMultOp64 : public PredMacroOp
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{
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protected:
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uint8_t eSize, dataSize, numStructElems, numRegs;
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bool wb;
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VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
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uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
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bool wb);
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};
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class VldSingleOp64 : public PredMacroOp
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{
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protected:
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uint8_t eSize, dataSize, numStructElems, index;
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bool wb, replicate;
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VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
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uint8_t dataSize, uint8_t numStructElems, uint8_t index,
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bool wb, bool replicate = false);
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};
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class VstSingleOp64 : public PredMacroOp
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{
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protected:
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uint8_t eSize, dataSize, numStructElems, index;
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bool wb, replicate;
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VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
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uint8_t dataSize, uint8_t numStructElems, uint8_t index,
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bool wb, bool replicate = false);
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};
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/**
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* Microops of the form
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* PC = IntRegA
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* CPSR = IntRegB
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*/
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class MicroSetPCCPSR : public MicroOp
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{
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protected:
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IntRegIndex ura, urb, urc;
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MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), urc(_urc)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Microops of the form IntRegA = IntRegB
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*/
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class MicroIntMov : public MicroOp
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{
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protected:
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RegIndex ura, urb;
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MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Microops of the form IntRegA = IntRegB op Imm
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*/
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class MicroIntImmOp : public MicroOp
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{
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protected:
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RegIndex ura, urb;
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int32_t imm;
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MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, int32_t _imm)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), imm(_imm)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MicroIntImmXOp : public MicroOpX
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{
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protected:
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RegIndex ura, urb;
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int64_t imm;
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MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, int64_t _imm)
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: MicroOpX(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), imm(_imm)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Microops of the form IntRegA = IntRegB op IntRegC
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*/
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class MicroIntOp : public MicroOp
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{
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protected:
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RegIndex ura, urb, urc;
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MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, RegIndex _urc)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), urc(_urc)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MicroIntRegXOp : public MicroOp
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{
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protected:
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RegIndex ura, urb, urc;
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ArmExtendType type;
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uint32_t shiftAmt;
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MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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ArmExtendType _type, uint32_t _shiftAmt)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), urc(_urc),
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type(_type), shiftAmt(_shiftAmt)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Microops of the form IntRegA = IntRegB op shifted IntRegC
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*/
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class MicroIntRegOp : public MicroOp
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{
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protected:
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RegIndex ura, urb, urc;
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int32_t shiftAmt;
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ArmShiftType shiftType;
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MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, RegIndex _urc,
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int32_t _shiftAmt, ArmShiftType _shiftType)
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), urc(_urc),
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shiftAmt(_shiftAmt), shiftType(_shiftType)
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{
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}
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};
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/**
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* Memory microops which use IntReg + Imm addressing
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*/
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class MicroMemOp : public MicroIntImmOp
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{
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protected:
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bool up;
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unsigned memAccessFlags;
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MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
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: MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
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up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for microcoded integer memory instructions.
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*/
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class MacroMemOp : public PredMacroOp
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{
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protected:
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MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex rn, bool index, bool up, bool user,
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bool writeback, bool load, uint32_t reglist);
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};
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/**
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* Base class for pair load/store instructions.
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*/
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class PairMemOp : public PredMacroOp
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{
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public:
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enum AddrMode {
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AddrMd_Offset,
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AddrMd_PreIndex,
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AddrMd_PostIndex
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};
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protected:
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PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
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bool exclusive, bool acrel, int64_t imm, AddrMode mode,
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IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
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};
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class BigFpMemImmOp : public PredMacroOp
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{
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protected:
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BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
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};
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class BigFpMemPostOp : public PredMacroOp
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{
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protected:
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BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
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};
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class BigFpMemPreOp : public PredMacroOp
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{
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protected:
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BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
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};
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class BigFpMemRegOp : public PredMacroOp
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{
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protected:
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BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool load, IntRegIndex dest, IntRegIndex base,
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IntRegIndex offset, ArmExtendType type, int64_t imm);
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};
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class BigFpMemLitOp : public PredMacroOp
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{
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protected:
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BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex dest, int64_t imm);
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};
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/**
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* Base classes for microcoded integer memory instructions.
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*/
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class VldMultOp : public PredMacroOp
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{
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protected:
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VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
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unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
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};
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class VldSingleOp : public PredMacroOp
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{
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protected:
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VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool all, unsigned elems, RegIndex rn, RegIndex vd,
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unsigned regs, unsigned inc, uint32_t size,
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uint32_t align, RegIndex rm, unsigned lane);
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};
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/**
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* Base class for microcoded integer memory instructions.
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*/
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class VstMultOp : public PredMacroOp
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{
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protected:
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VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
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unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
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};
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class VstSingleOp : public PredMacroOp
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{
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protected:
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VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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bool all, unsigned elems, RegIndex rn, RegIndex vd,
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unsigned regs, unsigned inc, uint32_t size,
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uint32_t align, RegIndex rm, unsigned lane);
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};
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/**
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* Base class for microcoded floating point memory instructions.
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*/
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class MacroVFPMemOp : public PredMacroOp
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{
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protected:
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MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex rn, RegIndex vd, bool single, bool up,
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bool writeback, bool load, uint32_t offset);
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};
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}
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#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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