612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
167 lines
5.6 KiB
C++
167 lines
5.6 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_BRANCH64_HH__
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#define __ARCH_ARM_INSTS_BRANCH64_HH__
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#include "arch/arm/insts/static_inst.hh"
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namespace ArmISA
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{
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// Branch to a target computed with an immediate
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class BranchImm64 : public ArmStaticInst
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{
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protected:
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int64_t imm;
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public:
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BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int64_t _imm) :
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ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
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{}
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ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Conditionally Branch to a target computed with an immediate
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class BranchImmCond64 : public BranchImm64
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{
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protected:
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ConditionCode condCode;
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public:
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BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int64_t _imm, ConditionCode _condCode) :
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BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Branch to a target computed with a register
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class BranchReg64 : public ArmStaticInst
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{
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protected:
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IntRegIndex op1;
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public:
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BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1) :
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ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Ret instruction
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class BranchRet64 : public BranchReg64
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{
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public:
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BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1) :
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BranchReg64(mnem, _machInst, __opClass, _op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Eret instruction
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class BranchEret64 : public ArmStaticInst
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{
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public:
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BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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ArmStaticInst(mnem, _machInst, __opClass)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Branch to a target computed with an immediate and a register
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class BranchImmReg64 : public ArmStaticInst
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{
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protected:
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int64_t imm;
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IntRegIndex op1;
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public:
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BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int64_t _imm, IntRegIndex _op1) :
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ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
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{}
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ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// Branch to a target computed with two immediates
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class BranchImmImmReg64 : public ArmStaticInst
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{
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protected:
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int64_t imm1;
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int64_t imm2;
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IntRegIndex op1;
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public:
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BranchImmImmReg64(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, int64_t _imm1, int64_t _imm2,
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IntRegIndex _op1) :
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ArmStaticInst(mnem, _machInst, __opClass),
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imm1(_imm1), imm2(_imm2), op1(_op1)
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{}
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ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}
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#endif //__ARCH_ARM_INSTS_BRANCH_HH__
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