12d903a650
can specify either independently.
python/m5/objects/Device.py:
io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently.
dma_bus defaults to point to whatever pio_bus uses.
--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
126 lines
4.4 KiB
C++
126 lines
4.4 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* System Console Interface
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*/
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#ifndef __ALPHA_CONSOLE_HH__
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#define __ALPHA_CONSOLE_HH__
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#include "base/range.hh"
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#include "dev/alpha_access.h"
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#include "dev/io_device.hh"
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#include "sim/host.hh"
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#include "sim/sim_object.hh"
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class BaseCPU;
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class SimConsole;
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class System;
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class SimpleDisk;
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/**
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* Memory mapped interface to the system console. This device
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* represents a shared data region between the OS Kernel and the
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* System Console.
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*
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* The system console is a small standalone program that is initially
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* run when the system boots. It contains the necessary code to
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* access the boot disk, to read/write from the console, and to pass
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* boot parameters to the kernel.
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*
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* This version of the system console is very different from the one
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* that would be found in a real system. Many of the functions use
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* some sort of backdoor to get their job done. For example, reading
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* from the boot device on a real system would require a minimal
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* device driver to access the disk controller, but since we have a
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* simulator here, we are able to bypass the disk controller and
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* access the disk image directly. There are also some things like
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* reading the kernel off the disk image into memory that are normally
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* taken care of by the console that are now taken care of by the
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* simulator.
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*
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* These shortcuts are acceptable since the system console is
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* primarily used doing boot before the kernel has loaded its device
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* drivers.
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*/
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class AlphaConsole : public PioDevice
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{
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protected:
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struct Access : public AlphaAccess
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{
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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union {
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Access *alphaAccess;
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uint8_t *consoleData;
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};
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/** the disk must be accessed from the console */
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SimpleDisk *disk;
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/** the system console (the terminal) is accessable from the console */
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SimConsole *console;
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/** a pointer to the system we are running in */
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System *system;
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/** a pointer to the CPU boot cpu */
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BaseCPU *cpu;
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Addr addr;
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static const Addr size = 0x80; // equal to sizeof(alpha_access);
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public:
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/** Standard Constructor */
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AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
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System *s, BaseCPU *c, Platform *platform,
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MemoryController *mmu, Addr addr,
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HierParams *hier, Bus *pio_bus);
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virtual void startup();
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/**
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* memory mapped reads and writes
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* standard serialization routines for checkpointing
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*/
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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public:
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __ALPHA_CONSOLE_HH__
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