89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
421 lines
44 KiB
Text
421 lines
44 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 13008791 # Number of BTB hits
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global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
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global.BPredUnit.lookups 19468548 # Number of BP lookups
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global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
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host_inst_rate 179748 # Simulator instruction rate (inst/s)
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host_mem_usage 209188 # Number of bytes of host memory used
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host_seconds 468.32 # Real time elapsed on the host
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host_tick_rate 87159490 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 84179709 # Number of instructions simulated
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sim_seconds 0.040819 # Number of seconds simulated
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sim_ticks 40818658500 # Number of ticks simulated
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system.cpu.commit.COM:branches 10240685 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 73457196
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 36278941 4938.79%
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1 18156304 2471.68%
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2 7455517 1014.95%
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3 3880419 528.26%
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4 2046448 278.59%
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5 1301140 177.13%
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6 721823 98.26%
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7 760802 103.57%
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8 2855802 388.77%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 91903055 # Number of instructions committed
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system.cpu.commit.COM:loads 20034413 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 26537108 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 84179709 # Number of Instructions Simulated
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system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
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system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 29894354 # number of overall hits
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system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 9171 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 159 # number of replacements
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system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use
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system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 105 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 31911121 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 31454022 # DTB hits
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system.cpu.dtb.misses 457099 # DTB misses
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system.cpu.dtb.read_accesses 24718123 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 24262026 # DTB read hits
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system.cpu.dtb.read_misses 456097 # DTB read misses
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system.cpu.dtb.write_accesses 7192998 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 7191996 # DTB write hits
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system.cpu.dtb.write_misses 1002 # DTB write misses
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system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched
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system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 81528343
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system.cpu.fetch.rateDist.min_value 0
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0 50560378 6201.57%
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1 3114212 381.98%
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2 2012618 246.86%
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3 3505366 429.96%
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4 4590613 563.07%
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5 1506961 184.84%
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6 2028359 248.79%
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7 1846743 226.52%
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8 12363093 1516.42%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
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system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses
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system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 19218965 # number of overall hits
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system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses
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system.cpu.icache.overall_misses 11038 # number of overall misses
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system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 8143 # number of replacements
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system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use
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system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
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system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
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system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value
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system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 65837672 # num instructions producing a value
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system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
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system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed
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system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed
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system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations
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system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly
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system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle
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system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads
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system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0.start_dist
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No_OpClass 7 0.00% # Type of FU issued
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IntAlu 64430040 61.93% # Type of FU issued
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IntMult 475055 0.46% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2782164 2.67% # Type of FU issued
|
|
FloatCmp 115645 0.11% # Type of FU issued
|
|
FloatCvt 2377276 2.29% # Type of FU issued
|
|
FloatMult 305748 0.29% # Type of FU issued
|
|
FloatDiv 755245 0.73% # Type of FU issued
|
|
FloatSqrt 323 0.00% # Type of FU issued
|
|
MemRead 25462424 24.48% # Type of FU issued
|
|
MemWrite 7324714 7.04% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 274346 14.19% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 31 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 6547 0.34% # attempts to use FU when none available
|
|
FloatMult 2333 0.12% # attempts to use FU when none available
|
|
FloatDiv 832912 43.09% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 743147 38.44% # attempts to use FU when none available
|
|
MemWrite 73812 3.82% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 35305774 4330.49%
|
|
1 18904885 2318.81%
|
|
2 11574997 1419.75%
|
|
3 6762756 829.50%
|
|
4 5075415 622.53%
|
|
5 2394533 293.71%
|
|
6 1208963 148.29%
|
|
7 250769 30.76%
|
|
8 50251 6.16%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 19230073 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 19230003 # ITB hits
|
|
system.cpu.itb.misses 70 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 7186 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 5110 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 81637318 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|