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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson b63631536d stats: Cumulative stats update 
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.541686 # Number of seconds simulated
sim_ticks 541686426500 # Number of ticks simulated
final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 146656 # Simulator instruction rate (inst/s)
host_op_rate 163606 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51433162 # Simulator tick rate (ticks/s)
host_mem_usage 242412 # Number of bytes of host memory used
host_seconds 10531.85 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory
system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory
system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 143773696 # Total number of bytes read from memory
system.physmem.bytesWritten 70430528 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
system.physmem.totGap 541686363500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 2246464 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1100477 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation
system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests
system.physmem.totBusLat 11229325000 # Total cycles spent in databus access
system.physmem.totBankLat 62918281250 # Total cycles spent in bank access
system.physmem.avgQLat 22389.56 # Average queueing delay per request
system.physmem.avgBankLat 28015.17 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 55404.72 # Average memory access latency
system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.09 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.23 # Average read queue length over time
system.physmem.avgWrQLen 10.65 # Average write queue length over time
system.physmem.readRowHits 1005654 # Number of row buffer hits during reads
system.physmem.writeRowHits 343066 # Number of row buffer hits during writes
system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes
system.physmem.avgGap 161845.21 # Average gap between requests
system.membus.throughput 395439408 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1420071 # Transaction distribution
system.membus.trans_dist::ReadResp 1420070 # Transaction distribution
system.membus.trans_dist::Writeback 1100477 # Transaction distribution
system.membus.trans_dist::ReadExReq 826393 # Transaction distribution
system.membus.trans_dist::ReadExResp 826393 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 214204160 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.9 # Layer utilization (%)
system.cpu.branchPred.lookups 304298989 # Number of BP lookups
system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups
system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1083372854 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed
system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked
system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 862 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued
system.cpu.iq.rate 1.864551 # Inst issue rate
system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 99 # number of nop insts executed
system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed
system.cpu.iew.exec_branches 238317780 # Number of branches executed
system.cpu.iew.exec_stores 190212225 # Number of stores executed
system.cpu.iew.exec_rate 1.836053 # Inst execution rate
system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1295814578 # num instructions producing a value
system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773814 # Number of memory references committed
system.cpu.commit.loads 485926769 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462426 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3001900611 # The number of ROB reads
system.cpu.rob.rob_writes 4481254115 # The number of ROB writes
system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads
system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads
system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes
system.cpu.fp_regfile_reads 91 # number of floating regfile reads
system.cpu.fp_regfile_writes 89 # number of floating regfile writes
system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%)
system.cpu.icache.tags.replacements 22 # number of replacements
system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits
system.cpu.icache.overall_hits::total 290622345 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses
system.cpu.icache.overall_misses::total 1216 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59439751 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59439751 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59439751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59439751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59439751 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59439751 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76009.911765 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76009.911765 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 2213775 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3782769 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3782769 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1067024 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1067024 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7356604 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7356633 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7356604 # number of overall hits
system.cpu.l2cache.overall_hits::total 7356633 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 753 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1419326 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1420079 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 826393 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 826393 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 753 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2245719 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2246472 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 753 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2245719 # number of overall misses
system.cpu.l2cache.overall_misses::total 2246472 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58361250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138416431000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 138474792250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84266311250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 84266311250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58361250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 222682742250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 222741103500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58361250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 222682742250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 222741103500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7708906 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7709688 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3782769 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3782769 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9602323 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9603105 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9602323 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9603105 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962916 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184115 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.184194 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436456 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436456 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962916 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233872 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.233932 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962916 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233872 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.233932 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77504.980080 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97522.648778 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 97512.034366 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101968.810542 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101968.810542 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 99151.515576 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 99151.515576 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1100477 # number of writebacks
system.cpu.l2cache.writebacks::total 1100477 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 752 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419319 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1420071 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826393 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 826393 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 752 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2245712 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2246464 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 9598226 # number of replacements
system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits
system.cpu.dcache.overall_hits::total 655929494 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses
system.cpu.dcache.overall_misses::total 17133418 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks
system.cpu.dcache.writebacks::total 3782769 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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