309e1d8193
TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
164 lines
5.6 KiB
C++
164 lines
5.6 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Decleration of a bus object.
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*/
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#ifndef __MEM_BUS_HH__
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#define __MEM_BUS_HH__
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#include <string>
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#include <list>
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#include <inttypes.h>
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#include "base/range.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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class Bus : public MemObject
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{
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/** a globally unique id for this bus. */
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int busId;
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struct DevMap {
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int portId;
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Range<Addr> range;
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};
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std::vector<DevMap> portList;
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/** Function called by the port when the bus is recieving a Timing
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transaction.*/
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bool recvTiming(Packet &pkt);
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/** Function called by the port when the bus is recieving a Atomic
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transaction.*/
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Tick recvAtomic(Packet &pkt);
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/** Function called by the port when the bus is recieving a Functional
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transaction.*/
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void recvFunctional(Packet &pkt);
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/** Function called by the port when the bus is recieving a status change.*/
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void recvStatusChange(Port::Status status, int id);
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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* @param id Id of the port this packet was received from (to prevent
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* loops)
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* @return pointer to port that the packet should be sent out of.
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*/
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Port *findPort(Addr addr, int id);
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/** Process address range request.
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* @param resp addresses that we can respond to
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* @param snoop addresses that we would like to snoop
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* @param id ide of the busport that made the request.
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*/
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void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
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/** Decleration of the buses port type, one will be instantiated for each
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of the interfaces connecting to the bus. */
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class BusPort : public Port
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{
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/** A pointer to the bus to which this port belongs. */
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Bus *bus;
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/** A id to keep track of the intercafe ID this port is connected to. */
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int id;
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public:
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/** Constructor for the BusPort.*/
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BusPort(Bus *_bus, int _id)
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: bus(_bus), id(_id)
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{ }
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protected:
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/** When reciving a timing request from the peer port (at id),
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pass it to the bus. */
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virtual bool recvTiming(Packet &pkt)
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{ pkt.src = id; return bus->recvTiming(pkt); }
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/** When reciving a Atomic requestfrom the peer port (at id),
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pass it to the bus. */
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virtual Tick recvAtomic(Packet &pkt)
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{ pkt.src = id; return bus->recvAtomic(pkt); }
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/** When reciving a Functional requestfrom the peer port (at id),
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pass it to the bus. */
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virtual void recvFunctional(Packet &pkt)
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{ pkt.src = id; bus->recvFunctional(pkt); }
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/** When reciving a status changefrom the peer port (at id),
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pass it to the bus. */
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virtual void recvStatusChange(Status status)
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{ bus->recvStatusChange(status, id); }
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// This should return all the 'owned' addresses that are
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// downstream from this bus, yes? That is, the union of all
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// the 'owned' address ranges of all the other interfaces on
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// this bus...
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{ bus->addressRanges(resp, snoop, id); }
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// Hack to make translating port work without changes
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virtual int deviceBlockSize() { return 32; }
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};
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/** An array of pointers to the peer port interfaces
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connected to this bus.*/
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std::vector<Port*> interfaces;
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public:
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/** A function used to return the port associated with this bus object. */
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virtual Port *getPort(const std::string &if_name)
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{
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// if_name ignored? forced to be empty?
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int id = interfaces.size();
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interfaces.push_back(new BusPort(this, id));
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return interfaces.back();
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}
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virtual void init();
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Bus(const std::string &n, int bus_id)
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: MemObject(n), busId(bus_id) {}
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};
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#endif //__MEM_BUS_HH__
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