89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
417 lines
44 KiB
Text
417 lines
44 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 806 # Number of BTB hits
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global.BPredUnit.BTBLookups 1937 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted
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global.BPredUnit.lookups 2263 # Number of BP lookups
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global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
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host_inst_rate 68343 # Simulator instruction rate (inst/s)
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host_mem_usage 200684 # Number of bytes of host memory used
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host_seconds 0.09 # Real time elapsed on the host
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host_tick_rate 133183507 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6386 # Number of instructions simulated
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 12474500 # Number of ticks simulated
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system.cpu.commit.COM:branches 1051 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 12416
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 9513 7661.89%
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1 1627 1310.41%
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2 488 393.04%
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3 267 215.05%
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4 153 123.23%
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5 104 83.76%
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6 96 77.32%
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7 53 42.69%
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8 115 92.62%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 6403 # Number of instructions committed
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system.cpu.commit.COM:loads 1185 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2050 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 6386 # Number of Instructions Simulated
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system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
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system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2104 # number of overall hits
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system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 554 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 2951 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 2890 # DTB hits
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system.cpu.dtb.misses 61 # DTB misses
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system.cpu.dtb.read_accesses 1876 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 1840 # DTB read hits
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system.cpu.dtb.read_misses 36 # DTB read misses
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system.cpu.dtb.write_accesses 1075 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 1050 # DTB write hits
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system.cpu.dtb.write_misses 25 # DTB write misses
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system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
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system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 13314
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system.cpu.fetch.rateDist.min_value 0
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0 10844 8144.81%
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1 252 189.27%
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2 238 178.76%
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3 230 172.75%
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4 272 204.30%
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5 162 121.68%
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6 232 174.25%
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7 129 96.89%
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8 955 717.29%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses
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system.cpu.icache.demand_misses 424 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1378 # number of overall hits
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system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses
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system.cpu.icache.overall_misses 424 # number of overall misses
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system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use
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system.cpu.icache.total_refs 1378 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 1450 # Number of branches executed
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system.cpu.iew.EXEC:nop 82 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate
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system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 1077 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 6020 # num instructions consuming a value
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system.cpu.iew.WB:count 8734 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 4491 # num instructions producing a value
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system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle
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system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed
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system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed
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system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
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system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly
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system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle
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system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads
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system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0.start_dist
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No_OpClass 2 0.02% # Type of FU issued
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IntAlu 6254 66.92% # Type of FU issued
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IntMult 1 0.01% # Type of FU issued
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IntDiv 0 0.00% # Type of FU issued
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FloatAdd 2 0.02% # Type of FU issued
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FloatCmp 0 0.00% # Type of FU issued
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FloatCvt 0 0.00% # Type of FU issued
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FloatMult 0 0.00% # Type of FU issued
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FloatDiv 0 0.00% # Type of FU issued
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FloatSqrt 0 0.00% # Type of FU issued
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MemRead 1986 21.25% # Type of FU issued
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MemWrite 1100 11.77% # Type of FU issued
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IprAccess 0 0.00% # Type of FU issued
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InstPrefetch 0 0.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0.end_dist
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system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 14 13.33% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 56 53.33% # attempts to use FU when none available
|
|
MemWrite 35 33.33% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 13314
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 9113 6844.67%
|
|
1 1716 1288.87%
|
|
2 1071 804.42%
|
|
3 725 544.54%
|
|
4 355 266.64%
|
|
5 172 129.19%
|
|
6 115 86.38%
|
|
7 34 25.54%
|
|
8 13 9.76%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 1838 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 1802 # ITB hits
|
|
system.cpu.itb.misses 36 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 24950 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|