gem5/arch/mips/isa
Korey Sewell 5cfc5e8080 The first fully coded version of decoder.isa!!!!!
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-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.

--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
2006-02-10 03:27:19 -05:00
..
formats Code for more "BasicOp" instructions ... formats for all instructions in place ... Edits to Branch Format 2006-02-08 16:24:04 -05:00
bitfields.isa name changes ... minor IntOP format change 2006-02-07 18:36:08 -05:00
decoder.isa The first fully coded version of decoder.isa!!!!! 2006-02-10 03:27:19 -05:00
formats.isa name changes ... minor IntOP format change 2006-02-07 18:36:08 -05:00
includes.isa name changes ... minor IntOP format change 2006-02-07 18:36:08 -05:00
main.isa add at least BasicOp Format to most if not all instructions 2006-02-08 14:50:07 -05:00
operands.isa name changes ... minor IntOP format change 2006-02-07 18:36:08 -05:00