4f430e9ab5
arch/mips/isa/bitfields.isa:
add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
Make unimplemented instructions Fail instead of just Warn
Edits to SRA & SRAV instructions
Implement CFC1 instructions
Unaligned Memory Access Support (Maybe Not fully functional yet)
Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
Fix disassembly
arch/mips/isa/formats/int.isa:
Add sign extend Immediate and zero extend Immediate to Int class.
Probably a bit unnecessary in the long run since these manipulations could
be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
Add inst2string function to Unimplemented panic. PRints out the instruction
binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
change return values to 32 instead of 64
arch/mips/linux_process.cc:
assign some syscalls to the right functions
cpu/static_inst.hh:
more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
toward a better implementation for unaligned memory access
mem/request.hh:
NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
additional SyscallVerbose comments
--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
132 lines
3.6 KiB
C++
132 lines
3.6 KiB
C++
// -*- mode:c++ -*-
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Integer operate instructions
|
|
//
|
|
|
|
//Outputs to decoder.hh
|
|
output header {{
|
|
#include <iostream>
|
|
using namespace std;
|
|
/**
|
|
* Base class for integer operations.
|
|
*/
|
|
class IntOp : public MipsStaticInst
|
|
{
|
|
protected:
|
|
|
|
/// Constructor
|
|
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
|
MipsStaticInst(mnem, _machInst, __opClass)
|
|
{
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
};
|
|
|
|
class IntImmOp : public MipsStaticInst
|
|
{
|
|
protected:
|
|
|
|
int16_t imm;
|
|
int32_t sextImm;
|
|
uint32_t zextImm;
|
|
|
|
/// Constructor
|
|
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
|
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
|
|
sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
|
|
{
|
|
//If Bit 15 is 1 then Sign Extend
|
|
int32_t temp = sextImm & 0x00008000;
|
|
if (temp > 0 && mnemonic != "lui") {
|
|
sextImm |= 0xFFFF0000;
|
|
}
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
|
|
|
|
};
|
|
|
|
}};
|
|
|
|
//Outputs to decoder.cc
|
|
output decoder {{
|
|
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
|
{
|
|
std::stringstream ss;
|
|
|
|
ccprintf(ss, "%-10s ", mnemonic);
|
|
|
|
// just print the first dest... if there's a second one,
|
|
// it's generally implicit
|
|
if (_numDestRegs > 0) {
|
|
printReg(ss, _destRegIdx[0]);
|
|
}
|
|
|
|
ss << ",";
|
|
|
|
// just print the first two source regs... if there's
|
|
// a third one, it's a read-modify-write dest (Rc),
|
|
// e.g. for CMOVxx
|
|
if (_numSrcRegs > 0) {
|
|
printReg(ss, _srcRegIdx[0]);
|
|
}
|
|
|
|
if (_numSrcRegs > 1) {
|
|
ss << ",";
|
|
printReg(ss, _srcRegIdx[1]);
|
|
}
|
|
|
|
return ss.str();
|
|
}
|
|
|
|
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
|
{
|
|
std::stringstream ss;
|
|
|
|
ccprintf(ss, "%-10s ", mnemonic);
|
|
|
|
if (_numDestRegs > 0) {
|
|
printReg(ss, _destRegIdx[0]);
|
|
}
|
|
|
|
ss << ",";
|
|
|
|
if (_numSrcRegs > 0) {
|
|
printReg(ss, _srcRegIdx[0]);
|
|
ss << ",";
|
|
}
|
|
|
|
if( mnemonic == "lui")
|
|
ccprintf(ss, "%08p ", sextImm);
|
|
else
|
|
ss << (int) sextImm;
|
|
|
|
return ss.str();
|
|
}
|
|
|
|
}};
|
|
|
|
//Used by decoder.isa
|
|
def format IntOp(code, *opt_flags) {{
|
|
orig_code = code
|
|
cblk = CodeBlock(code)
|
|
|
|
# Figure out if we are creating a IntImmOp or a IntOp
|
|
# by looking at the instruction name
|
|
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
|
|
strlen = len(name)
|
|
if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
|
|
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
|
|
|
|
header_output = BasicDeclare.subst(iop)
|
|
decoder_output = BasicConstructor.subst(iop)
|
|
decode_block = OperateNopCheckDecode.subst(iop)
|
|
exec_output = BasicExecute.subst(iop)
|
|
}};
|
|
|
|
|
|
|