e2dbe59f5d
In order for a system object to work in SE mode and FS mode, it has to either always require a platform object even in SE mode, or get rid of the requirement all together. Making SE mode carry around unnecessary/unused bits of FS seems less than ideal, so I decided to go with the second option. The platform pointer in the System class was used for exactly one purpose, a path for the Alpha Linux system object to get to the real time clock and read its frequency so that it could short cut the loops_per_jiffy calculation. There was also a copy and pasted implementation in MIPS, but since it was only there because it was there in Alpha I still count that as one use. This change reverses the mechanism that communicates the RTC frequency so that the Tsunami platform object pushes it up to the AlphaSystem object. This is slightly less specific than it could be because really only the AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform class was no longer necessary (and unimplemented on anything but Alpha) it was eliminated. After this change, a platform will need to have a system, but a system won't have to have a platform.
175 lines
4.6 KiB
C++
175 lines
4.6 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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/** @file
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* Implementation of PC platform.
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "arch/x86/intmessage.hh"
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#include "arch/x86/x86_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/intr_control.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8254.hh"
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#include "dev/x86/i8259.hh"
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#include "dev/x86/pc.hh"
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#include "dev/x86/south_bridge.hh"
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#include "dev/terminal.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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Pc::Pc(const Params *p)
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: Platform(p), system(p->system)
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{
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southBridge = NULL;
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}
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void
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Pc::init()
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{
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assert(southBridge);
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/*
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* Initialize the timer.
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*/
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I8254 & timer = *southBridge->pit;
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//Timer 0, mode 2, no bcd, 16 bit count
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timer.writeControl(0x34);
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//Timer 0, latch command
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timer.writeControl(0x00);
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//Write a 16 bit count of 0
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timer.writeCounter(0, 0);
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timer.writeCounter(0, 0);
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/*
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* Initialize the I/O APIC.
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*/
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I82094AA & ioApic = *southBridge->ioApic;
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I82094AA::RedirTableEntry entry = 0;
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entry.deliveryMode = DeliveryMode::ExtInt;
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entry.vector = 0x20;
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ioApic.writeReg(0x10, entry.bottomDW);
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ioApic.writeReg(0x11, entry.topDW);
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entry.deliveryMode = DeliveryMode::Fixed;
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entry.vector = 0x24;
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ioApic.writeReg(0x18, entry.bottomDW);
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ioApic.writeReg(0x19, entry.topDW);
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entry.mask = 1;
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entry.vector = 0x21;
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ioApic.writeReg(0x12, entry.bottomDW);
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ioApic.writeReg(0x13, entry.topDW);
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entry.vector = 0x20;
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ioApic.writeReg(0x14, entry.bottomDW);
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ioApic.writeReg(0x15, entry.topDW);
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entry.vector = 0x28;
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ioApic.writeReg(0x20, entry.bottomDW);
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ioApic.writeReg(0x21, entry.topDW);
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entry.vector = 0x2C;
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ioApic.writeReg(0x28, entry.bottomDW);
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ioApic.writeReg(0x29, entry.topDW);
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entry.vector = 0x2E;
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ioApic.writeReg(0x2C, entry.bottomDW);
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ioApic.writeReg(0x2D, entry.topDW);
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entry.vector = 0x30;
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ioApic.writeReg(0x30, entry.bottomDW);
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ioApic.writeReg(0x31, entry.topDW);
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/*
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* Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
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* these out and masked them before passing control to the OS.
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*/
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southBridge->pic1->maskAll();
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southBridge->pic2->maskAll();
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}
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void
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Pc::postConsoleInt()
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{
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southBridge->ioApic->signalInterrupt(4);
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southBridge->pic1->signalInterrupt(4);
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}
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void
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Pc::clearConsoleInt()
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{
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warn_once("Don't know what interrupt to clear for console.\n");
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//panic("Need implementation\n");
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}
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void
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Pc::postPciInt(int line)
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{
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southBridge->ioApic->signalInterrupt(line);
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}
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void
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Pc::clearPciInt(int line)
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{
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warn_once("Tried to clear PCI interrupt %d\n", line);
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}
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Addr
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Pc::pciToDma(Addr pciAddr) const
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{
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return pciAddr;
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}
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Addr
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Pc::calcPciConfigAddr(int bus, int dev, int func)
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{
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assert(func < 8);
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assert(dev < 32);
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assert(bus == 0);
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return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
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}
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Addr
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Pc::calcPciIOAddr(Addr addr)
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{
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return PhysAddrPrefixIO + addr;
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}
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Addr
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Pc::calcPciMemAddr(Addr addr)
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{
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return addr;
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}
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Pc *
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PcParams::create()
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{
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return new Pc(this);
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}
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