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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
Andreas Hansson d9193d1b20 stats: Match current behaviour 
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 51.278333 # Number of seconds simulated
sim_ticks 51278333141000 # Number of ticks simulated
final_tick 51278333141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 303802 # Simulator instruction rate (inst/s)
host_op_rate 357005 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 18317890976 # Simulator tick rate (ticks/s)
host_mem_usage 688280 # Number of bytes of host memory used
host_seconds 2799.36 # Real time elapsed on the host
sim_insts 850450745 # Number of instructions simulated
sim_ops 999383448 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 82048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 86080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2553908 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 18749896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 26560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 25408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 451200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4994624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 34432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 29952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1461952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 6681856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 70784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 53120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1684864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 11657408 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 398592 # Number of bytes read from this memory
system.physmem.bytes_read::total 49042684 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2553908 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 451200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1461952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1684864 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6151924 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 68500992 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 68521572 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1345 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 80312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 292980 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 415 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 397 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7050 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 78041 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 538 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 468 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 22843 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 104404 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1106 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 830 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 26326 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 182147 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6228 # Number of read requests responded to by this memory
system.physmem.num_reads::total 806712 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1070328 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1072901 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1679 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 49805 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 365649 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 518 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 495 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 8799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 97402 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 584 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 28510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 130306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 32857 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 227336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7773 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 956402 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 49805 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 8799 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 28510 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 32857 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 119971 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1335866 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1336268 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1335866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1679 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 49805 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 366051 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 495 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 8799 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 97402 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 584 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 28510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 130306 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 32857 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 227336 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7773 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2292669 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 428538 # Number of read requests accepted
system.physmem.writeReqs 456847 # Number of write requests accepted
system.physmem.readBursts 428538 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 456847 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 27408320 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue
system.physmem.bytesWritten 29236416 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 27426432 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 29238208 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 26649 # Per bank write bursts
system.physmem.perBankRdBursts::1 30049 # Per bank write bursts
system.physmem.perBankRdBursts::2 26532 # Per bank write bursts
system.physmem.perBankRdBursts::3 25500 # Per bank write bursts
system.physmem.perBankRdBursts::4 26079 # Per bank write bursts
system.physmem.perBankRdBursts::5 32966 # Per bank write bursts
system.physmem.perBankRdBursts::6 25199 # Per bank write bursts
system.physmem.perBankRdBursts::7 25237 # Per bank write bursts
system.physmem.perBankRdBursts::8 24838 # Per bank write bursts
system.physmem.perBankRdBursts::9 28373 # Per bank write bursts
system.physmem.perBankRdBursts::10 26870 # Per bank write bursts
system.physmem.perBankRdBursts::11 27983 # Per bank write bursts
system.physmem.perBankRdBursts::12 26309 # Per bank write bursts
system.physmem.perBankRdBursts::13 25787 # Per bank write bursts
system.physmem.perBankRdBursts::14 24479 # Per bank write bursts
system.physmem.perBankRdBursts::15 25405 # Per bank write bursts
system.physmem.perBankWrBursts::0 27847 # Per bank write bursts
system.physmem.perBankWrBursts::1 29934 # Per bank write bursts
system.physmem.perBankWrBursts::2 27360 # Per bank write bursts
system.physmem.perBankWrBursts::3 28363 # Per bank write bursts
system.physmem.perBankWrBursts::4 28817 # Per bank write bursts
system.physmem.perBankWrBursts::5 32577 # Per bank write bursts
system.physmem.perBankWrBursts::6 27869 # Per bank write bursts
system.physmem.perBankWrBursts::7 28879 # Per bank write bursts
system.physmem.perBankWrBursts::8 27745 # Per bank write bursts
system.physmem.perBankWrBursts::9 30902 # Per bank write bursts
system.physmem.perBankWrBursts::10 28100 # Per bank write bursts
system.physmem.perBankWrBursts::11 29746 # Per bank write bursts
system.physmem.perBankWrBursts::12 27536 # Per bank write bursts
system.physmem.perBankWrBursts::13 27471 # Per bank write bursts
system.physmem.perBankWrBursts::14 26272 # Per bank write bursts
system.physmem.perBankWrBursts::15 27401 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 51277332920000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 428538 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 456847 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 325583 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 70650 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20024 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8787 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 367 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 675 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 413 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 211 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 80 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 80 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 71 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 67 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 581 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 552 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 10375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 12229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 21178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 22558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 25424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 25687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 25579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 25980 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 26739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 26656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 27115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 28437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 27753 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 28093 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 29855 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 26497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 26161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 25503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 521 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 267353 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 211.870778 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 133.094335 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 252.016088 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 129551 48.46% 48.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 69660 26.06% 74.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 23971 8.97% 83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11874 4.44% 87.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 7888 2.95% 90.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4787 1.79% 92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3806 1.42% 94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2811 1.05% 95.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13005 4.86% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 267353 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 24743 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.307279 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 12.628838 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31 23085 93.30% 93.30% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63 1534 6.20% 99.50% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95 94 0.38% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127 12 0.05% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159 6 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-191 2 0.01% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255 1 0.00% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::288-319 1 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-543 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 24743 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 24743 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.462555 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.679981 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.466510 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 17 0.07% 0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 18 0.07% 0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 7 0.03% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 50 0.20% 0.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 22406 90.55% 90.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1021 4.13% 95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 245 0.99% 96.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 205 0.83% 96.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 59 0.24% 97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 45 0.18% 97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 91 0.37% 97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 19 0.08% 97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 158 0.64% 98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 47 0.19% 98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 11 0.04% 98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 29 0.12% 98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 119 0.48% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 17 0.07% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 15 0.06% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 48 0.19% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 83 0.34% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 2 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 4 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 24743 # Writes before turning the bus around for reads
system.physmem.totQLat 8299174160 # Total ticks spent queuing
system.physmem.totMemAccLat 16328955410 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2141275000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19379.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 38129.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.57 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 5.79 # Average write queue length when enqueuing
system.physmem.readRowHits 313353 # Number of row buffer hits during reads
system.physmem.writeRowHits 304366 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.62 # Row buffer hit rate for writes
system.physmem.avgGap 57915294.39 # Average gap between requests
system.physmem.pageHitRate 69.79 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1033164720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 562076625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1701999000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1501066080 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1179927426690 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 30447593029500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34942675148055 # Total energy per rank (pJ)
system.physmem_0.averagePower 665.942257 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48866965519857 # Time in different power states
system.physmem_0.memoryStateTime::REF 1692411240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 123966214393 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 988023960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 537516375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1638335400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1459121040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1177251222825 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29686423716000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34178654321040 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.571395 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48870902891583 # Time in different power states
system.physmem_1.memoryStateTime::REF 1692411240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 120022768167 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 90231 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 90231 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 90231 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 90231 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 90231 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.527073 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -205000507008 -52.71% -52.71% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 593941627000 152.71% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 388941119992 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 65649 84.67% 84.67% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11889 15.33% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 77538 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90231 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90231 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77538 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77538 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 167769 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 64940650 # DTB read hits
system.cpu0.dtb.read_misses 68234 # DTB read misses
system.cpu0.dtb.write_hits 59349095 # DTB write hits
system.cpu0.dtb.write_misses 21997 # DTB write misses
system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 40980 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2794 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 7599 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 65008884 # DTB read accesses
system.cpu0.dtb.write_accesses 59371092 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 124289745 # DTB hits
system.cpu0.dtb.misses 90231 # DTB misses
system.cpu0.dtb.accesses 124379976 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 52885 # Table walker walks requested
system.cpu0.itb.walker.walksLong 52885 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 52885 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 52885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 52885 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.527164 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -205035740008 -52.72% -52.72% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 593976860000 152.72% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 388941119992 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 45865 94.85% 94.85% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2491 5.15% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 48356 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52885 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52885 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48356 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48356 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 101241 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 347148099 # ITB inst hits
system.cpu0.itb.inst_misses 52885 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 28527 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 347200984 # ITB inst accesses
system.cpu0.itb.hits 347148099 # DTB hits
system.cpu0.itb.misses 52885 # DTB misses
system.cpu0.itb.accesses 347200984 # DTB accesses
system.cpu0.numCycles 418851699 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16522 # number of quiesce instructions executed
system.cpu0.committedInsts 347002044 # Number of instructions committed
system.cpu0.committedOps 408295196 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 375110913 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 357489 # Number of float alu accesses
system.cpu0.num_func_calls 20952666 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 52632755 # number of instructions that are conditional controls
system.cpu0.num_int_insts 375110913 # number of integer instructions
system.cpu0.num_fp_insts 357489 # number of float instructions
system.cpu0.num_int_register_reads 548276980 # number of times the integer registers were read
system.cpu0.num_int_register_writes 297820090 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 571479 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 314936 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 90391371 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 90175878 # number of times the CC registers were written
system.cpu0.num_mem_refs 124362861 # number of memory refs
system.cpu0.num_load_insts 64997668 # Number of load instructions
system.cpu0.num_store_insts 59365193 # Number of store instructions
system.cpu0.num_idle_cycles 408653989.262248 # Number of idle cycles
system.cpu0.num_busy_cycles 10197709.737752 # Number of busy cycles
system.cpu0.not_idle_fraction 0.024347 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.975653 # Percentage of idle cycles
system.cpu0.Branches 77385391 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 283178336 69.32% 69.32% # Class of executed instruction
system.cpu0.op_class::IntMult 901174 0.22% 69.54% # Class of executed instruction
system.cpu0.op_class::IntDiv 41440 0.01% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 48921 0.01% 69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
system.cpu0.op_class::MemRead 64997668 15.91% 85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite 59365193 14.53% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 408532732 # Class of executed instruction
system.cpu0.dcache.tags.replacements 9687552 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 293952506 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9688064 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.341718 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.138446 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.125391 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.691064 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.044815 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970974 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010011 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009162 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.009853 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1245495121 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1245495121 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 60779853 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 18961352 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26111596 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 45441324 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 151294125 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56143457 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17475743 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23187165 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 37961445 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 134767810 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 158913 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47173 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75137 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 114608 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 395831 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 129155 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44895 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57683 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97740 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 329473 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1454318 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 433667 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579314 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933829 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3401128 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544855 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 472149 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 627026 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1076109 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3720139 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 116923310 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 36437095 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 49298761 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 83402769 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 286061935 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 117082223 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 36484268 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 49373898 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 83517377 # number of overall hits
system.cpu0.dcache.overall_hits::total 286457766 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2029256 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 653198 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 985570 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3497352 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7165376 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 851964 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 257580 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 600165 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3409601 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5119310 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 471821 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 150396 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 207281 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 345345 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1174843 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 677444 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 112505 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 152358 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 284476 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1226783 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91274 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38716 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47958 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 178987 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 356935 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 3 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2881220 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 910778 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1585735 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 6906953 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 12284686 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3353041 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1061174 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1793016 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7252298 # number of overall misses
system.cpu0.dcache.overall_misses::total 13459529 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10960907500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17114957500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 61176605000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 89252470000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9674205500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22728130500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118919824516 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 151322160516 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2777991000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 3811495000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 7834790952 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 14424276952 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 568655000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 714283000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2393915500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3676853500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 109000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 109000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 20635113000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 39843088000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 180096429516 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 240574630516 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 20635113000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 39843088000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 180096429516 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 240574630516 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62809109 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 19614550 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27097166 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 48938676 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 158459501 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56995421 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 17733323 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 23787330 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 41371046 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 139887120 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 630734 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 197569 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 282418 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 459953 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1570674 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 806599 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 157400 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 210041 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 382216 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1556256 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1545592 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 472383 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 627272 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1112816 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3758063 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1544857 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 472149 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 627026 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1076112 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3720144 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 119804530 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 37347873 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 50884496 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 90309722 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 298346621 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 120435264 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 37545442 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 51166914 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 90769675 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 299917295 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032308 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033302 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036372 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071464 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.045219 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014948 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014525 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025230 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082415 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.036596 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.748051 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761233 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.733951 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.750827 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747987 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839877 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714771 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.725373 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.744281 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788291 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059054 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081959 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076455 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160842 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094978 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024049 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024386 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031163 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076481 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041176 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027841 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028264 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.035042 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.079898 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.044877 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16780.375170 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17365.542275 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.264147 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.076276 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37558.061573 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37869.803304 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.929856 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.093025 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24692.155904 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 25016.704079 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27541.131596 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11757.806354 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14687.855150 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14893.928020 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13374.800963 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10301.185090 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 36333.333333 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21800 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22656.578222 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25125.943490 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26074.656873 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19583.295048 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19445.550871 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22221.267406 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24833.015620 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17873.926384 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 13201149 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 42765 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 880108 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 406 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.999465 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 105.332512 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 7502187 # number of writebacks
system.cpu0.dcache.writebacks::total 7502187 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3304 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 129070 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1937801 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2070175 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4910 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 266090 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2829152 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3100152 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 34 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2050 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2084 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8564 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10548 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 110240 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 129352 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8214 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 395160 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4766953 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5170327 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8214 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 395160 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4766953 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5170327 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 649894 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 856500 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1559551 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3065945 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 252670 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 334075 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580449 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1167194 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 150015 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 204632 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 338269 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 692916 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 112505 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 152324 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 282426 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 547255 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30152 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 37410 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 68747 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136309 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 902564 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 1190575 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2140000 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4233139 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1052579 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1395207 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2478269 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4926055 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6276 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6461 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6522 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19259 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5881 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5970 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6236 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18087 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 12157 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12431 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12758 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 37346 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10091751000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13620756000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26803800500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50516307500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9207058000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 12098027000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21802343152 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 43107428152 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3089558000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4271039000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6719235000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14079832000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2665486000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 3657832500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 7405729452 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 13729047952 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 402292000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 498531000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 981967500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1882790500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 106000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 106000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19298809000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25718783000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 48606143652 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 93623735652 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22388367000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29989822000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 55325378652 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 107703567652 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1244510500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1253007000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1222915500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3720433000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1201167500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1184957500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1195953455 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3582078455 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2445678000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2437964500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2418868955 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7302511455 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033133 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031608 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031867 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019348 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014248 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014044 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014030 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008344 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759304 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.724571 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.735443 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.441158 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714771 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.725211 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.738917 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.351648 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063830 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059639 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061778 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036271 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024166 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023398 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023696 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.014189 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028035 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027268 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027303 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.016425 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15528.303077 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15902.809107 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.870131 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.586338 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36439.062809 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36213.505949 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.169288 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.530626 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20594.993834 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20871.804019 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19863.584898 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20319.680885 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23692.155904 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 24013.500827 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 26221.840241 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 25087.112867 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13342.133192 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13326.142743 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14283.786929 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.664608 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 35333.333333 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35333.333333 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21382.205583 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21601.984755 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22713.151239 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22116.858353 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21270.011087 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21494.890722 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22324.202357 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21864.061130 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198296.765456 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193933.911159 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 187506.209752 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193178.929332 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204245.451454 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198485.343384 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 191782.144804 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198047.130812 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 201174.467385 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196119.740970 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 189596.249804 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195536.642612 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 15833780 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.971388 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 559992507 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15834292 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.365807 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11768020500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.662838 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.739189 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 21.951060 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.618302 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934888 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009256 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.042873 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012926 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 592023830 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 592023830 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 341615603 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 106621003 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 64011899 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 47744002 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 559992507 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 341615603 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 106621003 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 64011899 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 47744002 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 559992507 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 341615603 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 106621003 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 64011899 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 47744002 # number of overall hits
system.cpu0.icache.overall_hits::total 559992507 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5580852 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1667075 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3872640 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 5076367 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16196934 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5580852 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1667075 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3872640 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 5076367 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16196934 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5580852 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1667075 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3872640 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 5076367 # number of overall misses
system.cpu0.icache.overall_misses::total 16196934 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22554803500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53200018000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 68390400817 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 144145222317 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 22554803500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 53200018000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 68390400817 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 144145222317 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 22554803500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 53200018000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 68390400817 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 144145222317 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 347196455 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 108288078 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 67884539 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 52820369 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 576189441 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 347196455 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 108288078 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 67884539 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 52820369 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 576189441 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 347196455 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 108288078 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 67884539 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 52820369 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 576189441 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016074 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015395 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057047 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.096106 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028110 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016074 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015395 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057047 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.096106 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028110 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016074 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015395 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057047 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.096106 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028110 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.567356 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13737.403425 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13472.312151 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8899.537549 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13529.567356 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13737.403425 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13472.312151 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8899.537549 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.567356 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13737.403425 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13472.312151 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8899.537549 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 58905 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 3585 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.430962 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 15833780 # number of writebacks
system.cpu0.icache.writebacks::total 15833780 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 362545 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 362545 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 362545 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 362545 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 362545 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 362545 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1667075 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3872640 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4713822 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10253537 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1667075 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3872640 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4713822 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10253537 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1667075 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3872640 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4713822 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10253537 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 20887728500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49327378000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 60408755849 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 130623862349 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 20887728500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49327378000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 60408755849 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 130623862349 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 20887728500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49327378000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 60408755849 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 130623862349 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015395 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.057047 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.089243 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017795 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015395 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.057047 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.089243 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017795 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015395 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.057047 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.089243 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017795 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.567356 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12737.403425 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12739.395425 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.567356 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12737.403425 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12739.395425 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.567356 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12737.403425 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12739.395425 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 32812 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 32812 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4690 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 24112 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 32807 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 1.066845 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 193.234552 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 32806 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 32807 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 28807 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25324.695387 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21900.388938 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15981.091084 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 18461 64.09% 64.09% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 10165 35.29% 99.37% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 148 0.51% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 28807 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 2784865428 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.637616 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.480689 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1009190500 36.24% 36.24% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 1775674928 63.76% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 2784865428 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 24112 83.72% 83.72% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4690 16.28% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 28802 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32812 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32812 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28802 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28802 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 61614 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 20290778 # DTB read hits
system.cpu1.dtb.read_misses 25288 # DTB read misses
system.cpu1.dtb.write_hits 18371397 # DTB write hits
system.cpu1.dtb.write_misses 7524 # DTB write misses
system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 18352 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 2632 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20316066 # DTB read accesses
system.cpu1.dtb.write_accesses 18378921 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 38662175 # DTB hits
system.cpu1.dtb.misses 32812 # DTB misses
system.cpu1.dtb.accesses 38694987 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 20715 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 943 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18376 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 19319 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28783.140949 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25411.076231 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19382.499659 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 9731 50.37% 50.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 9374 48.52% 98.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 1 0.01% 98.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 168 0.87% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 22 0.11% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.05% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 19319 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 18376 95.12% 95.12% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 943 4.88% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 19319 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19319 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19319 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 40034 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 108288078 # ITB inst hits
system.cpu1.itb.inst_misses 20715 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13933 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 108308793 # ITB inst accesses
system.cpu1.itb.hits 108288078 # DTB hits
system.cpu1.itb.misses 20715 # DTB misses
system.cpu1.itb.accesses 108308793 # DTB accesses
system.cpu1.numCycles 1188105502 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 108209898 # Number of instructions committed
system.cpu1.committedOps 126974949 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 116708707 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 113927 # Number of float alu accesses
system.cpu1.num_func_calls 6429899 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16402371 # number of instructions that are conditional controls
system.cpu1.num_int_insts 116708707 # number of integer instructions
system.cpu1.num_fp_insts 113927 # number of float instructions
system.cpu1.num_int_register_reads 168563743 # number of times the integer registers were read
system.cpu1.num_int_register_writes 92548799 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 187994 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 86044 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 27990654 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 27915757 # number of times the CC registers were written
system.cpu1.num_mem_refs 38659204 # number of memory refs
system.cpu1.num_load_insts 20289811 # Number of load instructions
system.cpu1.num_store_insts 18369393 # Number of store instructions
system.cpu1.num_idle_cycles 1163060687.092743 # Number of idle cycles
system.cpu1.num_busy_cycles 25044814.907257 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021080 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978920 # Percentage of idle cycles
system.cpu1.Branches 24096387 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 88104313 69.34% 69.34% # Class of executed instruction
system.cpu1.op_class::IntMult 267805 0.21% 69.56% # Class of executed instruction
system.cpu1.op_class::IntDiv 10742 0.01% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 11023 0.01% 69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
system.cpu1.op_class::MemRead 20289811 15.97% 85.54% # Class of executed instruction
system.cpu1.op_class::MemWrite 18369393 14.46% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 127053129 # Class of executed instruction
system.cpu2.branchPred.lookups 39776917 # Number of BP lookups
system.cpu2.branchPred.condPredicted 27483460 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 2037436 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 28756518 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 19292729 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 67.089934 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4859404 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 317380 # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups 1168446 # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits 802318 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 366128 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 149530 # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.walker.walks 93967 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 93967 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6944 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29768 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 93967 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 93967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 93967 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 36712 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 25539.442144 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22201.127196 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 16823.219049 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767 24012 65.41% 65.41% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12449 33.91% 99.32% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839 190 0.52% 99.83% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607 24 0.07% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375 5 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 13 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::360448-393215 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-425983 6 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::425984-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 36712 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 29768 81.09% 81.09% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 6944 18.91% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 36712 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93967 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93967 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36712 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36712 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 130679 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 28283757 # DTB read hits
system.cpu2.dtb.read_misses 78317 # DTB read misses
system.cpu2.dtb.write_hits 24727017 # DTB write hits
system.cpu2.dtb.write_misses 15650 # DTB write misses
system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 22142 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 90 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2053 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 3761 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 28362074 # DTB read accesses
system.cpu2.dtb.write_accesses 24742667 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 53010774 # DTB hits
system.cpu2.dtb.misses 93967 # DTB misses
system.cpu2.dtb.accesses 53104741 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.walker.walks 27720 # Table walker walks requested
system.cpu2.itb.walker.walksLong 27720 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1832 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23079 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 27720 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 27720 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 27720 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 24911 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 29141.122396 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25972.278022 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 17945.677356 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 12737 51.13% 51.13% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 11873 47.66% 98.79% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.80% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 235 0.94% 99.74% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 24911 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 23079 92.65% 92.65% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1832 7.35% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 24911 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27720 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27720 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24911 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24911 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 52631 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 67934299 # ITB inst hits
system.cpu2.itb.inst_misses 27720 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 16373 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 46985 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 67962019 # ITB inst accesses
system.cpu2.itb.hits 67934299 # DTB hits
system.cpu2.itb.misses 27720 # DTB misses
system.cpu2.itb.accesses 67962019 # DTB accesses
system.cpu2.numCycles 6665035719 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 145016271 # Number of instructions committed
system.cpu2.committedOps 170167286 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 13691437 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1431 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 95890552078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 45.960606 # CPI: cycles per instruction
system.cpu2.ipc 0.021758 # IPC: instructions per cycle
system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu2.op_class_0::IntAlu 117737819 69.19% 69.19% # Class of committed instruction
system.cpu2.op_class_0::IntMult 373156 0.22% 69.41% # Class of committed instruction
system.cpu2.op_class_0::IntDiv 14991 0.01% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMisc 14732 0.01% 69.43% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
system.cpu2.op_class_0::MemRead 27395173 16.10% 85.53% # Class of committed instruction
system.cpu2.op_class_0::MemWrite 24631415 14.47% 100.00% # Class of committed instruction
system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.op_class_0::total 170167286 # Class of committed instruction
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.tickCycles 269996715 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 6395039004 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 74192352 # Number of BP lookups
system.cpu3.branchPred.condPredicted 49437452 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3347278 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 50136785 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 33881997 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 67.579118 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9625210 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 106045 # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups 2919697 # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits 1497835 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 1421862 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 235981 # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu3.dtb.walker.walks 504531 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 504531 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8579 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49642 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 315573 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 188958 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2466.701595 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 15451.703294 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535 187621 99.29% 99.29% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071 761 0.40% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607 388 0.21% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143 66 0.03% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679 68 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::720896-786431 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 188958 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 235670 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 22726.303730 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.636586 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.207208 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535 231036 98.03% 98.03% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3674 1.56% 99.59% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607 687 0.29% 99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143 78 0.03% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679 114 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751 37 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 235670 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -29346850516 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.109432 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -29931174016 101.99% 101.99% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 321600000 -1.10% 100.90% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 109899000 -0.37% 100.52% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 66660000 -0.23% 100.29% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 26916000 -0.09% 100.20% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 15037500 -0.05% 100.15% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 15685000 -0.05% 100.10% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 23345000 -0.08% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 4979000 -0.02% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 163000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 37500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 1500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -29346850516 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 49642 85.26% 85.26% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8579 14.74% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 58221 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 504531 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 504531 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58221 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58221 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 562752 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
system.cpu3.dtb.read_hits 58858607 # DTB read hits
system.cpu3.dtb.read_misses 345619 # DTB read misses
system.cpu3.dtb.write_hits 45337458 # DTB write hits
system.cpu3.dtb.write_misses 158912 # DTB write misses
system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 30161 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 96 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 4984 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults 31824 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 59204226 # DTB read accesses
system.cpu3.dtb.write_accesses 45496370 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
system.cpu3.dtb.hits 104196065 # DTB hits
system.cpu3.dtb.misses 504531 # DTB misses
system.cpu3.dtb.accesses 104700596 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu3.itb.walker.walks 57749 # Table walker walks requested
system.cpu3.itb.walker.walksLong 57749 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1869 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 39849 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8061 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 49688 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1392.157060 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 9705.040089 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767 49238 99.09% 99.09% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535 280 0.56% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303 20 0.04% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071 53 0.11% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839 71 0.14% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607 11 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 49688 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 49779 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 28899.797103 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 24686.192128 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 20239.281965 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-32767 26767 53.77% 53.77% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-65535 22147 44.49% 98.26% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-98303 258 0.52% 98.78% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::98304-131071 22 0.04% 98.82% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-163839 390 0.78% 99.61% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::163840-196607 115 0.23% 99.84% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-229375 17 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.89% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-294911 35 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-425983 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 49779 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -29349528016 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 0.914056 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev 0.275786 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 -2489826708 8.48% 8.48% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -26888510808 91.61% 100.10% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 25356500 -0.09% 100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 3132000 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 321000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -29349528016 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 39849 95.52% 95.52% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 1869 4.48% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 41718 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 57749 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 57749 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 41718 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 41718 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 99467 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 52942414 # ITB inst hits
system.cpu3.itb.inst_misses 57749 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 23395 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults 105407 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
system.cpu3.itb.inst_accesses 53000163 # ITB inst accesses
system.cpu3.itb.hits 52942414 # DTB hits
system.cpu3.itb.misses 57749 # DTB misses
system.cpu3.itb.accesses 53000163 # DTB accesses
system.cpu3.numCycles 367393110 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles 140035519 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 329019087 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 74192352 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 45005042 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 204823297 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7558478 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1392210 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 11060 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 2040 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 2559054 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 98792 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 5855 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 52820449 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2085044 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 22116 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 352706869 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.090104 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.342261 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 272076000 77.14% 77.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10117728 2.87% 80.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10161980 2.88% 82.89% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7427862 2.11% 85.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15229127 4.32% 89.31% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5034181 1.43% 90.74% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5424859 1.54% 92.28% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4755580 1.35% 93.63% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 22479552 6.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 352706869 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.201943 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.895551 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 114206086 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 168667065 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 59684206 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7159093 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2988451 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 11027683 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 801920 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 358900429 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2465138 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 2988451 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 118341629 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 14120881 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 134077735 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 62618980 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 20557126 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 350288916 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 64776 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1233598 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 933453 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 10294511 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 2108 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 333834443 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 533414827 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 412704170 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 534789 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 279088781 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 54745657 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 7872437 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 6763416 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 39440190 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 56882383 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 47659648 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7390317 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 8048428 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 332440192 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 7866599 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 331640119 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 487315 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 46360769 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 29124307 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 191271 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 352706869 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.940271 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.666990 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 224298657 63.59% 63.59% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 52689618 14.94% 78.53% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24223023 6.87% 85.40% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17391351 4.93% 90.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 12809979 3.63% 93.96% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9108183 2.58% 96.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6180606 1.75% 98.30% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3577681 1.01% 99.31% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2427771 0.69% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 352706869 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 1672825 25.77% 25.77% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 16469 0.25% 26.02% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1475 0.02% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.05% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2639879 40.67% 66.72% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2160482 33.28% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 224723694 67.76% 67.76% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 782210 0.24% 68.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 40081 0.01% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 289 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 42689 0.01% 68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 60119649 18.13% 86.15% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 45931480 13.85% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 331640119 # Type of FU issued
system.cpu3.iq.rate 0.902685 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6491130 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019573 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1022298212 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 386704326 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 319186755 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 667340 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 341320 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 298656 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 337775175 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 356047 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2654997 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 9481961 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 11664 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 384451 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 4830568 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 2150262 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 4167982 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 2988451 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 8896535 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 3943315 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 340388861 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 1005407 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 56882383 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 47659648 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6617026 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 121260 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 3776054 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 384451 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1420846 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1561965 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 2982811 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 327664673 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 58849807 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3477335 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 82070 # number of nop insts executed
system.cpu3.iew.exec_refs 104185879 # number of memory reference insts executed
system.cpu3.iew.exec_branches 60732264 # Number of branches executed
system.cpu3.iew.exec_stores 45336072 # Number of stores executed
system.cpu3.iew.exec_rate 0.891864 # Inst execution rate
system.cpu3.iew.wb_sent 320275931 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 319485411 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 157730975 # num instructions producing a value
system.cpu3.iew.wb_consumers 273958307 # num instructions consuming a value
system.cpu3.iew.wb_rate 0.869601 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.575748 # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts 46394137 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7675328 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2556293 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 344852948 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.852381 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.849144 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 238109143 69.05% 69.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 51559449 14.95% 84.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 18667514 5.41% 89.41% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8519895 2.47% 91.88% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6096374 1.77% 93.65% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3704494 1.07% 94.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3440464 1.00% 95.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2103815 0.61% 96.33% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12651800 3.67% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 344852948 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 250222532 # Number of instructions committed
system.cpu3.commit.committedOps 293946017 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 90229501 # Number of memory references committed
system.cpu3.commit.loads 47400421 # Number of loads committed
system.cpu3.commit.membars 1979442 # Number of memory barriers committed
system.cpu3.commit.branches 55926403 # Number of branches committed
system.cpu3.commit.fp_insts 287180 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 270155076 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7460078 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu 203036725 69.07% 69.07% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 612324 0.21% 69.28% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 30368 0.01% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 37099 0.01% 69.30% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 47400421 16.13% 85.43% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 42829080 14.57% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total 293946017 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12651800 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 670506126 # The number of ROB reads
system.cpu3.rob.rob_writes 688548433 # The number of ROB writes
system.cpu3.timesIdled 2399442 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 14686241 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98624955783 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 250222532 # Number of Instructions Simulated
system.cpu3.committedOps 293946017 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.468265 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.468265 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.681076 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.681076 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 385596565 # number of integer regfile reads
system.cpu3.int_regfile_writes 228796101 # number of integer regfile writes
system.cpu3.fp_regfile_reads 580685 # number of floating regfile reads
system.cpu3.fp_regfile_writes 358952 # number of floating regfile writes
system.cpu3.cc_regfile_reads 69302556 # number of cc regfile reads
system.cpu3.cc_regfile_writes 69940425 # number of cc regfile writes
system.cpu3.misc_regfile_reads 654940348 # number of misc regfile reads
system.cpu3.misc_regfile_writes 7733963 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40259 # Transaction distribution
system.iobus.trans_dist::ReadResp 40259 # Transaction distribution
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7491984 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 28447500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 82500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 12315500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 21455000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 262449133 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 54866000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 76206000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.420631 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13089104998009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 5.909087 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 4.511544 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.369318 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.281971 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039587 # Number of tag accesses
system.iocache.tags.data_accesses 1039587 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8806 # number of demand (read+write) misses
system.iocache.demand_misses::total 8846 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8806 # number of overall misses
system.iocache.overall_misses::total 8846 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 1073978422 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1073978422 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 6143621711 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 6143621711 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 1073978422 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1073978422 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 1073978422 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1073978422 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8806 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8846 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8806 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8846 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 121959.848058 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 121449.555807 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 57597.893488 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 57597.893488 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 121959.848058 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121408.367850 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 121959.848058 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121408.367850 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 21262 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 2148 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.898510 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 5707 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 5707 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 48856 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 48856 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 5707 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 5707 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 5707 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 5707 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 788628422 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 788628422 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3698645601 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3698645601 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 788628422 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 788628422 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 788628422 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 788628422 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648081 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.645369 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.458036 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.458036 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.648081 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.645150 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.648081 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.645150 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138186.161206 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138186.161206 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75705.043413 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75705.043413 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 138186.161206 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 138186.161206 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 138186.161206 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 138186.161206 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1158394 # number of replacements
system.l2c.tags.tagsinuse 65318.411237 # Cycle average of tags in use
system.l2c.tags.total_refs 47534578 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1221500 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 38.914923 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36632.144769 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.246189 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 202.168712 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4157.667973 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8742.110148 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.831722 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 47.900932 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 347.749800 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2205.430231 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 32.408854 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 51.307546 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1406.712197 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3461.981272 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 83.334747 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 114.561611 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2502.338392 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 5155.516141 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.558962 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002232 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003085 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.063441 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.133394 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000440 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000731 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.005306 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.033652 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000495 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000783 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.021465 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.052826 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001272 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.001748 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.038183 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.078667 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996680 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62843 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 261 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 560 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2808 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5049 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54318 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.958908 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 420535401 # Number of tag accesses
system.l2c.tags.data_accesses 420535401 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 157367 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 107004 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 58638 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 43521 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 153028 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 59170 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 293557 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 105792 # number of ReadReq hits
system.l2c.ReadReq_hits::total 978077 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 7502187 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 7502187 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 15831215 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 15831215 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 3881 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1299 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1589 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2641 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9410 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 649967 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 198078 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 263559 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 467871 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1579475 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5543628 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1660025 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3849796 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4687305 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15740754 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2482832 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 800663 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1056956 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1884656 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6225107 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 284770 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 92927 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 125862 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 228099 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 731658 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 157367 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 107004 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5543628 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3132799 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 58638 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 43521 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1660025 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 998741 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 153028 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 59170 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3849796 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1320515 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 293557 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 105792 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 4687305 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 2352527 # number of demand (read+write) hits
system.l2c.demand_hits::total 24523413 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 157367 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 107004 # number of overall hits
system.l2c.overall_hits::cpu0.inst 5543628 # number of overall hits
system.l2c.overall_hits::cpu0.data 3132799 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 58638 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 43521 # number of overall hits
system.l2c.overall_hits::cpu1.inst 1660025 # number of overall hits
system.l2c.overall_hits::cpu1.data 998741 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 153028 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 59170 # number of overall hits
system.l2c.overall_hits::cpu2.inst 3849796 # number of overall hits
system.l2c.overall_hits::cpu2.data 1320515 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 293557 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 105792 # number of overall hits
system.l2c.overall_hits::cpu3.inst 4687305 # number of overall hits
system.l2c.overall_hits::cpu3.data 2352527 # number of overall hits
system.l2c.overall_hits::total 24523413 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1282 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1345 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 415 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 397 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 538 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 468 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 1108 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 841 # number of ReadReq misses
system.l2c.ReadReq_misses::total 6394 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 14017 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4542 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 5830 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 9491 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 33880 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 184099 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48751 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 63154 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 102986 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 398990 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 37224 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 7050 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 22844 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 26326 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 93444 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 109519 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 29398 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 41529 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 79372 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 259818 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 392674 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 19578 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data 26462 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data 54327 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 493041 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1345 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 37224 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 293618 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 415 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 397 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 7050 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 78149 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 538 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 468 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 22844 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 104683 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker 1108 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker 841 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 26326 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 182358 # number of demand (read+write) misses
system.l2c.demand_misses::total 758646 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1282 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1345 # number of overall misses
system.l2c.overall_misses::cpu0.inst 37224 # number of overall misses
system.l2c.overall_misses::cpu0.data 293618 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 415 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 397 # number of overall misses
system.l2c.overall_misses::cpu1.inst 7050 # number of overall misses
system.l2c.overall_misses::cpu1.data 78149 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 538 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 468 # number of overall misses
system.l2c.overall_misses::cpu2.inst 22844 # number of overall misses
system.l2c.overall_misses::cpu2.data 104683 # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker 1108 # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker 841 # number of overall misses
system.l2c.overall_misses::cpu3.inst 26326 # number of overall misses
system.l2c.overall_misses::cpu3.data 182358 # number of overall misses
system.l2c.overall_misses::total 758646 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 56208500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 55753500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 72904000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 62985000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 151670000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker 115932500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 515453500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 179896500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 234675000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data 400123500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 814695000 # number of UpgradeReq miss cycles
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007028 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009040 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003503 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007847 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003753 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.007784 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003813 # mshr miss rate for ReadReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785820 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.782311 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.458836 # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.180406 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.108615 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.004229 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.005899 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005585 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003551 # mshr miss rate for ReadCleanReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.040411 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023176 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.174019 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.173722 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.192358 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.081952 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007028 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009040 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004229 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.072569 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003503 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007847 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005899 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.073449 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003753 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.007784 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005585 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.071938 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007028 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009040 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004229 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.072569 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003503 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007847 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005899 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.073449 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003753 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.007784 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005585 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.071938 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 126899.575386 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67928.885953 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 67995.883362 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68003.529660 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67984.216886 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68500 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120748.774384 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122278.660148 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137112.547472 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129040.689545 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120929.219858 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123907.941166 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126175.324242 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124596.150729 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123405.660215 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124798.388200 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131103.109627 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127855.477184 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67688.962100 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68484.657244 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68685.248587 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 68438.022458 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120929.219858 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121748.238608 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123907.941166 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123278.208361 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126175.324242 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134496.973058 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 128015.097468 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120929.219858 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121748.238608 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123907.941166 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123278.208361 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126175.324242 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134496.973058 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 128015.097468 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185790.073295 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181433.137285 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174998.236737 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180673.788878 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192745.451454 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186970.686767 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180273.412123 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186539.282247 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 189154.766801 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184092.550881 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 177576.696818 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 183514.499491 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 76738 # Transaction distribution
system.membus.trans_dist::ReadResp 445217 # Transaction distribution
system.membus.trans_dist::WriteReq 33648 # Transaction distribution
system.membus.trans_dist::WriteResp 33648 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1070328 # Transaction distribution
system.membus.trans_dist::CleanEvict 202542 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34555 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14337 # Transaction distribution
system.membus.trans_dist::ReadExReq 398389 # Transaction distribution
system.membus.trans_dist::ReadExResp 398389 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 368479 # Transaction distribution
system.membus.trans_dist::InvalidateReq 599634 # Transaction distribution
system.membus.trans_dist::InvalidateResp 450461 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3699064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3828461 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 295887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4124348 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 110365024 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 110534446 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7279360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 117813806 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2019 # Total snoops (count)
system.membus.snoop_fanout::samples 2784335 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 2784335 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2784335 # Request fanout histogram
system.membus.reqLayer0.occupancy 62370000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1759502 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 3098675220 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 2309466891 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 28779324 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 51706902 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26184437 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 3148 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2316 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2316 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 1482882 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23802645 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 7959053 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 15833779 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2295611 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 43290 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 43295 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1978465 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1978465 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15834389 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6490632 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1273555 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1224699 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47588616 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29285291 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 809621 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1728313 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79411841 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2026923028 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022015642 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2929800 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6124520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3057992990 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1664727 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 38155395 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.016407 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.127033 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 37529393 98.36% 98.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 626002 1.64% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 38155395 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 30930828488 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 835176 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 15386050434 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 7871932216 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 287489224 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 705270826 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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