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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Andreas Hansson d9193d1b20 stats: Match current behaviour 
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.827390 # Number of seconds simulated
sim_ticks 2827390179000 # Number of ticks simulated
final_tick 2827390179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 115301 # Simulator instruction rate (inst/s)
host_op_rate 139868 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2711751203 # Simulator tick rate (ticks/s)
host_mem_usage 622004 # Number of bytes of host memory used
host_seconds 1042.64 # Real time elapsed on the host
sim_insts 120217407 # Number of instructions simulated
sim_ops 145833000 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1297536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1327400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8611392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 181424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 629012 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 447552 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12497708 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1297536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 181424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1478960 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8852800 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8870364 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22521 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 21261 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 134553 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2903 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9849 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6993 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 198133 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 138325 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142716 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 634 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 458916 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 469479 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 3045703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 64167 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 222471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 158292 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4420228 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 458916 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 64167 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 523083 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3131085 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3137297 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3131085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 458916 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 475677 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 3045703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 64167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 222485 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 158292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7557525 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198134 # Number of read requests accepted
system.physmem.writeReqs 142716 # Number of write requests accepted
system.physmem.readBursts 198134 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 142716 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
system.physmem.bytesWritten 8883264 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12497772 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8870364 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12497 # Per bank write bursts
system.physmem.perBankRdBursts::1 12182 # Per bank write bursts
system.physmem.perBankRdBursts::2 12917 # Per bank write bursts
system.physmem.perBankRdBursts::3 12745 # Per bank write bursts
system.physmem.perBankRdBursts::4 14769 # Per bank write bursts
system.physmem.perBankRdBursts::5 12267 # Per bank write bursts
system.physmem.perBankRdBursts::6 12449 # Per bank write bursts
system.physmem.perBankRdBursts::7 12406 # Per bank write bursts
system.physmem.perBankRdBursts::8 12316 # Per bank write bursts
system.physmem.perBankRdBursts::9 12005 # Per bank write bursts
system.physmem.perBankRdBursts::10 11767 # Per bank write bursts
system.physmem.perBankRdBursts::11 10930 # Per bank write bursts
system.physmem.perBankRdBursts::12 12080 # Per bank write bursts
system.physmem.perBankRdBursts::13 12638 # Per bank write bursts
system.physmem.perBankRdBursts::14 12372 # Per bank write bursts
system.physmem.perBankRdBursts::15 11644 # Per bank write bursts
system.physmem.perBankWrBursts::0 9110 # Per bank write bursts
system.physmem.perBankWrBursts::1 9003 # Per bank write bursts
system.physmem.perBankWrBursts::2 9525 # Per bank write bursts
system.physmem.perBankWrBursts::3 9146 # Per bank write bursts
system.physmem.perBankWrBursts::4 8599 # Per bank write bursts
system.physmem.perBankWrBursts::5 8760 # Per bank write bursts
system.physmem.perBankWrBursts::6 8787 # Per bank write bursts
system.physmem.perBankWrBursts::7 8590 # Per bank write bursts
system.physmem.perBankWrBursts::8 8640 # Per bank write bursts
system.physmem.perBankWrBursts::9 8402 # Per bank write bursts
system.physmem.perBankWrBursts::10 8397 # Per bank write bursts
system.physmem.perBankWrBursts::11 7923 # Per bank write bursts
system.physmem.perBankWrBursts::12 8683 # Per bank write bursts
system.physmem.perBankWrBursts::13 8738 # Per bank write bursts
system.physmem.perBankWrBursts::14 8625 # Per bank write bursts
system.physmem.perBankWrBursts::15 7873 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
system.physmem.totGap 2827389912000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 551 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3087 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 194468 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 138325 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 63072 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 74912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13439 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8664 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6556 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4708 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1378 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 855 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 259 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4835 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9851 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9885 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 12144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1397 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 90813 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 237.346812 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 134.326622 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 300.184335 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 49078 54.04% 54.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17700 19.49% 73.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6123 6.74% 80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3320 3.66% 83.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2774 3.05% 86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1638 1.80% 88.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 995 1.10% 89.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 978 1.08% 90.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8207 9.04% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90813 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 29.444230 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 548.218856 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6721 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.642623 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.824239 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.739703 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5581 83.00% 83.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 483 7.18% 90.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 96 1.43% 91.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 46 0.68% 92.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 45 0.67% 92.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 26 0.39% 93.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 56 0.83% 94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 16 0.24% 94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 112 1.67% 96.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 17 0.25% 96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.07% 96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 15 0.22% 96.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 76 1.13% 97.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.07% 97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.07% 97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 30 0.45% 98.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 72 1.07% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 5 0.07% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 3 0.04% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.01% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.10% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 2 0.03% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.04% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
system.physmem.totQLat 6642491804 # Total ticks spent queuing
system.physmem.totMemAccLat 10354691804 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
system.physmem.avgQLat 33550.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 52300.65 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 28.40 # Average write queue length when enqueuing
system.physmem.readRowHits 165266 # Number of row buffer hits during reads
system.physmem.writeRowHits 80705 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 58.14 # Row buffer hit rate for writes
system.physmem.avgGap 8295114.90 # Average gap between requests
system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 797401800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 463449600 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 80516584620 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1625805455250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1892805688350 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.453328 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2704566595208 # Time in different power states
system.physmem_0.memoryStateTime::REF 94412760000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 28410820792 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 329774760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 179936625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 746865600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 435980880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 80145816435 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626130690500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1892640423360 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.394877 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2705113148361 # Time in different power states
system.physmem_1.memoryStateTime::REF 94412760000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 27864169139 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 53911245 # Number of BP lookups
system.cpu0.branchPred.condPredicted 24947324 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 985007 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 32642222 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 14256732 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 43.675740 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15584760 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 34685 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 10159968 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 9991718 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 168250 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 52822 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 71875 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 71875 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26071 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21701 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 24103 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 47772 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 520.796701 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 3158.268863 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 46423 97.18% 97.18% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 981 2.05% 99.23% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 165 0.35% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 25 0.05% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 47772 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 18721 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9623.609798 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 9038.861696 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 18593 99.32% 99.32% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 88 0.47% 99.79% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 16 0.09% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 18721 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 87200107652 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.546732 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.508218 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 39687331700 45.51% 45.51% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 47447148952 54.41% 99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2 30000500 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::3 16923500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4 5972000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::5 3342500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6 3974500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::7 1269500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8 992000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::9 652500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::11 287500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12 887500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14 101000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::15 441500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 87200107652 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5974 77.64% 77.64% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1720 22.36% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 7694 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71875 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71875 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7694 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7694 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 79569 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 24391036 # DTB read hits
system.cpu0.dtb.read_misses 61424 # DTB read misses
system.cpu0.dtb.write_hits 18141184 # DTB write hits
system.cpu0.dtb.write_misses 10451 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3871 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 259 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2351 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 984 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 24452460 # DTB read accesses
system.cpu0.dtb.write_accesses 18151635 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 42532220 # DTB hits
system.cpu0.dtb.misses 71875 # DTB misses
system.cpu0.dtb.accesses 42604095 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 11562 # Table walker walks requested
system.cpu0.itb.walker.walksShort 11562 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4001 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6396 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 1165 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 10397 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 461.575454 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2367.707906 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9981 96.00% 96.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 185 1.78% 97.78% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 127 1.22% 99.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.57% 99.57% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.67% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.22% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 10397 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 4031 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5265.028524 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383 3778 93.72% 93.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767 218 5.41% 99.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151 33 0.82% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 4031 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 22774753212 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.815515 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.388020 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 4202728000 18.45% 18.45% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 18570993712 81.54% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 925000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 106500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22774753212 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2507 87.47% 87.47% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 359 12.53% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2866 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11562 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11562 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2866 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2866 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 14428 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 74050785 # ITB inst hits
system.cpu0.itb.inst_misses 11562 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 74062347 # ITB inst accesses
system.cpu0.itb.hits 74050785 # DTB hits
system.cpu0.itb.misses 11562 # DTB misses
system.cpu0.itb.accesses 74062347 # DTB accesses
system.cpu0.numCycles 210807967 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 21220653 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 200130599 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 53911245 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 39833210 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 180362708 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 5820684 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 154995 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 66964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 420974 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 452324 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 103497 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 74050081 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 272746 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 5705 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 205692457 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.188766 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.306289 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 98524588 47.90% 47.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 31037557 15.09% 62.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 14908217 7.25% 70.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 61222095 29.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 205692457 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.255736 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.949350 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26429213 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 111222366 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 60319076 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 5157963 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2563839 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3171648 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 350947 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 158388827 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4014782 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 2563839 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 35280795 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 13301493 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 85153816 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 56482950 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 12909564 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 141500597 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1085672 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1524488 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 177088 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 62946 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 8550384 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 145816753 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 652563275 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 157207618 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 11000 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 133932927 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11883815 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 2738789 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 2591099 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 23044959 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 25364147 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 19673316 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1767343 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2535257 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 138424520 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1769995 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 136412034 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 484040 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11120854 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 22999814 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 127192 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 205692457 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.663184 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.962224 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 126945183 61.72% 61.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 34499506 16.77% 78.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 31998886 15.56% 94.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 11080832 5.39% 99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1167990 0.57% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 60 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 205692457 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 11130033 43.82% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 71 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5937286 23.38% 67.20% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8330186 32.80% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 91960000 67.41% 67.42% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 113905 0.08% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8243 0.01% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 25115664 18.41% 85.92% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 19211906 14.08% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 136412034 # Type of FU issued
system.cpu0.iq.rate 0.647091 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 25397576 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 504359597 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 151322890 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 132769388 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 38543 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 13252 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 11438 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 161782111 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 25184 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 383563 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2036205 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2638 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 20853 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 948035 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 126036 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 394781 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2563839 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1921080 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 231914 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 140382056 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 25364147 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 19673316 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 906447 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 31018 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 175567 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 20853 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 275420 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 424017 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 699437 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 135325292 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 24646519 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1015002 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 187541 # number of nop insts executed
system.cpu0.iew.exec_refs 43690093 # number of memory reference insts executed
system.cpu0.iew.exec_branches 26111417 # Number of branches executed
system.cpu0.iew.exec_stores 19043574 # Number of stores executed
system.cpu0.iew.exec_rate 0.641936 # Inst execution rate
system.cpu0.iew.wb_sent 134725872 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 132780826 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 67751819 # num instructions producing a value
system.cpu0.iew.wb_consumers 109549817 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.629866 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.618457 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 10037586 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1642803 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 638504 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 202442995 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.638330 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.339217 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 140546392 69.43% 69.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 34245976 16.92% 86.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 12926596 6.39% 92.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3383235 1.67% 94.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 4977119 2.46% 96.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 2872114 1.42% 98.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1322991 0.65% 98.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 578946 0.29% 99.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1589626 0.79% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 202442995 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 106684229 # Number of instructions committed
system.cpu0.commit.committedOps 129225495 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 42053222 # Number of memory references committed
system.cpu0.commit.loads 23327941 # Number of loads committed
system.cpu0.commit.membars 666720 # Number of memory barriers committed
system.cpu0.commit.branches 25467916 # Number of branches committed
system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 112793765 # Number of committed integer instructions.
system.cpu0.commit.function_calls 4892953 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 87052485 67.36% 67.36% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 111545 0.09% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8243 0.01% 67.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 23327941 18.05% 85.51% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 18725281 14.49% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 129225495 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1589626 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 316721982 # The number of ROB reads
system.cpu0.rob.rob_writes 281765642 # The number of ROB writes
system.cpu0.timesIdled 131866 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 5115510 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5443972636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 106532386 # Number of Instructions Simulated
system.cpu0.committedOps 129073652 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.978816 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.978816 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.505353 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.505353 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 146797472 # number of integer regfile reads
system.cpu0.int_regfile_writes 83857123 # number of integer regfile writes
system.cpu0.fp_regfile_reads 9583 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu0.cc_regfile_reads 477737826 # number of cc regfile reads
system.cpu0.cc_regfile_writes 51222601 # number of cc regfile writes
system.cpu0.misc_regfile_reads 282455977 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1264842 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 752726 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.858519 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 38773458 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 753238 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.475706 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.858519 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966521 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966521 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 83704103 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 83704103 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 22086605 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 22086605 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15435818 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15435818 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316186 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 316186 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 372593 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 372593 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370988 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 370988 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 37522423 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 37522423 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 37838609 # number of overall hits
system.cpu0.dcache.overall_hits::total 37838609 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 688506 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 688506 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1977745 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1977745 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 154100 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 154100 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25656 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25656 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20273 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20273 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2666251 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2666251 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2820351 # number of overall misses
system.cpu0.dcache.overall_misses::total 2820351 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9974637500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 9974637500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36928416860 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 36928416860 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417346500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 417346500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 525290500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 525290500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 179000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 179000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 46903054360 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 46903054360 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 46903054360 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 46903054360 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 22775111 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 22775111 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 17413563 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 17413563 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470286 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 470286 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 398249 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 398249 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391261 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 391261 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 40188674 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 40188674 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 40658960 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 40658960 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030231 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.030231 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113575 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.113575 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327673 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327673 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064422 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064422 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051815 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051815 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066343 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.066343 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069366 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.069366 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16267.013564 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17591.387443 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16630.218849 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 989 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 5684279 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 212555 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.019231 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 26.742627 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 752726 # number of writebacks
system.cpu0.dcache.writebacks::total 752726 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276877 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 276877 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1641015 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1641015 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18966 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18966 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1917892 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1917892 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1917892 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1917892 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411629 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 411629 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336730 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 336730 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107461 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 107461 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6690 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6690 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20273 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20273 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 748359 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 748359 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 855820 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 855820 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31816 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60315 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149646500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149646500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7737247391 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7737247391 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800196500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800196500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108932500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108932500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 505022500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 505022500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 174000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12886893891 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 12886893891 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14687090391 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 14687090391 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623903000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623903000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395425500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395425500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12019328500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019328500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018074 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018074 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019337 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019337 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228501 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228501 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016799 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051815 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051815 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018621 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.018621 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021049 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.021049 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12510.407430 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22977.600425 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22977.600425 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16752.091456 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.091456 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16282.884903 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24911.088640 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24911.088640 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17220.202992 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17220.202992 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17161.424588 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17161.424588 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208194.084737 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208194.084737 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189319.818239 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189319.818239 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199275.942966 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1311471 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.728689 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 72677991 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1311983 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 55.395528 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 8207383000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728689 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 149404895 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 149404895 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 72677991 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 72677991 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 72677991 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 72677991 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 72677991 # number of overall hits
system.cpu0.icache.overall_hits::total 72677991 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1368448 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1368448 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1368448 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1368448 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1368448 # number of overall misses
system.cpu0.icache.overall_misses::total 1368448 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14924586060 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14924586060 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14924586060 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14924586060 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14924586060 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14924586060 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 74046439 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 74046439 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 74046439 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 74046439 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 74046439 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 74046439 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018481 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.018481 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018481 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.018481 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018481 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.018481 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10906.213506 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10906.213506 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1977903 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 120515 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.412090 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 1311471 # number of writebacks
system.cpu0.icache.writebacks::total 1311471 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56430 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 56430 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 56430 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 56430 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 56430 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 56430 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312018 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1312018 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312018 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1312018 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312018 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1312018 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13396366068 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 13396366068 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13396366068 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 13396366068 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13396366068 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 13396366068 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017719 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017719 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017719 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10210.504786 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1932548 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1935408 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2604 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 246016 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 282767 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16108.615116 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 3429175 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 298912 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 11.472189 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14681.579143 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.440463 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.496999 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1415.098510 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.896092 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000698 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086371 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.983192 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15155 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 298 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4586 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7902 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2036 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924988 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 69610425 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 69610425 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60495 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13905 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 74400 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 507703 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 507703 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1523854 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1523854 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 206993 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 206993 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258247 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1258247 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 428473 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 428473 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60495 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13905 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1258247 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 635466 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1968113 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60495 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13905 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1258247 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 635466 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1968113 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 354 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 125 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 479 # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55429 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55429 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20273 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20273 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74521 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 74521 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 53742 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 53742 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97171 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 97171 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 354 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 125 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 53742 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 171692 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 225913 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 354 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 125 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 53742 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 171692 # number of overall misses
system.cpu0.l2cache.overall_misses::total 225913 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11980000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3266000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 15246000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 178815000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 178815000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41943500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41943500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 166500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 166500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4097480997 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 4097480997 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3752300498 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3752300498 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3420930498 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3420930498 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11980000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3266000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3752300498 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 7518411495 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 11285957993 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11980000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3266000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3752300498 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 7518411495 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 11285957993 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60849 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14030 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 74879 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507704 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 507704 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1523854 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1523854 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55429 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55429 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20273 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20273 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281514 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 281514 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1311989 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1311989 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 525644 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 525644 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60849 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14030 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1311989 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 807158 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2194026 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60849 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14030 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1311989 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 807158 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2194026 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.008909 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.006397 # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.264715 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.264715 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040962 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040962 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184861 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184861 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.008909 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040962 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.212712 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.102967 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.008909 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040962 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.212712 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.102967 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26128 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31828.810021 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3226.018871 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3226.018871 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2068.934050 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2068.934050 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54984.246011 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54984.246011 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69820.633732 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69820.633732 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35205.261837 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35205.261837 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 49957.098498 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 49957.098498 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 204 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.unused_prefetches 10407 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 233202 # number of writebacks
system.cpu0.l2cache.writebacks::total 233202 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
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system.cpu0.l2cache.ReadExReq_mshr_hits::total 32963 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 774 # number of ReadSharedReq MSHR hits
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system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33737 # number of demand (read+write) MSHR hits
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system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33737 # number of overall MSHR hits
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system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 125 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 478 # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
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system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262414 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 262414 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55429 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55429 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20273 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20273 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41558 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 41558 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 53700 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 53700 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96397 # number of ReadSharedReq MSHR misses
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system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53700 # number of demand (read+write) MSHR misses
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system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34819 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
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system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63318 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of ReadReq MSHR miss cycles
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system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12357000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 22141788258 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1433561500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1433561500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 351805000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 351805000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 136500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 136500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2493972500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2493972500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3428273498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3428273498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2782772498 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2782772498 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2516000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3428273498 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5276744998 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 8717375496 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2516000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3428273498 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5276744998 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 30859163754 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398052500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369072500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6767125000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178546465 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178546465 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398052500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547618965 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945671465 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006384 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147623 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147623 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040930 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.183388 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.183388 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.087571 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207175 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests 4281853 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162712 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32662 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 328300 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3848 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 121117 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2006967 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 741466 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1556492 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 207602 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 320187 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 85477 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42629 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113152 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 299842 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 296502 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312018 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 596340 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3402 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3941483 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739757 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30823 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130322 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6842385 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167949424 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104071122 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56120 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243396 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 272320062 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 1018529 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3250936 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.119239 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.327701 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 2867147 88.19% 88.19% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 379941 11.69% 99.88% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 3848 0.12% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3250936 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 4282821452 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 113625688 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1971630792 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1296047217 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 16802481 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 69515913 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 3871087 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2220502 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 213805 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 1955914 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 1266404 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 64.747428 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 774472 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 5638 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 216728 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 192718 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 24010 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 5536 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 15135 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 15135 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8000 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3062 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 4073 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 11062 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 636.232146 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3393.246458 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 10520 95.10% 95.10% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 182 1.65% 96.75% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 208 1.88% 98.63% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 44 0.40% 99.02% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 10 0.09% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 20 0.18% 99.29% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.04% 99.33% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.57% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.05% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 11062 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 3287 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 7252.269841 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383 2804 85.31% 85.31% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767 438 13.33% 98.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.06% 99.70% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535 8 0.24% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 3287 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 78326908560 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.188289 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.393350 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 63608298256 81.21% 81.21% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 14703547304 18.77% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 10074500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 1868000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 997000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 536500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 1004000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 156000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 32000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 91000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 15500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 43500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 105500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 9000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 4500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 126000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 78326908560 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1232 71.42% 71.42% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 493 28.58% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1725 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15135 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15135 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1725 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1725 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 16860 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 3481626 # DTB read hits
system.cpu1.dtb.read_misses 13250 # DTB read misses
system.cpu1.dtb.write_hits 2942267 # DTB write hits
system.cpu1.dtb.write_misses 1885 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1665 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 44 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 3494876 # DTB read accesses
system.cpu1.dtb.write_accesses 2944152 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 6423893 # DTB hits
system.cpu1.dtb.misses 15135 # DTB misses
system.cpu1.dtb.accesses 6439028 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 5379 # Table walker walks requested
system.cpu1.itb.walker.walksShort 5379 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2691 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2153 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 535 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 4844 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 218.414533 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 1692.156629 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 4709 97.21% 97.21% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 42 0.87% 98.08% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 42 0.87% 98.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 13 0.27% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 10 0.21% 99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 7 0.14% 99.57% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.08% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.10% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-18431 2 0.04% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 6 0.12% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 4844 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1373 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 9997.704100 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5248.867098 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 278 20.25% 20.25% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1006 73.27% 93.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 56 4.08% 97.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 1.17% 98.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.66% 99.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.36% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1373 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 18192386416 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.925541 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.262684 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1355392264 7.45% 7.45% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 16836194152 92.55% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 800000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 18192386416 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 695 82.94% 82.94% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 143 17.06% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 838 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5379 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5379 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 838 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 838 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 6965528 # ITB inst hits
system.cpu1.itb.inst_misses 5379 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 902 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 384 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 6970907 # ITB inst accesses
system.cpu1.itb.hits 6965528 # DTB hits
system.cpu1.itb.misses 5379 # DTB misses
system.cpu1.itb.accesses 6970907 # DTB accesses
system.cpu1.numCycles 32092744 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 7782299 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 20640770 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3871087 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2233594 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 22614955 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 645830 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 74008 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 29636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 160010 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 275842 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 16624 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 6964682 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 92359 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 1934 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 31276289 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.805380 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.188121 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 19613481 62.71% 62.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 4233968 13.54% 76.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1331194 4.26% 80.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 6097646 19.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 31276289 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.120622 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.643160 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 6336736 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 16565133 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 7246187 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 914830 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 213403 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 597831 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 111765 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 19357447 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 835377 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 213403 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 7521212 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2374588 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11566982 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 6962571 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2637533 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 18397316 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 130089 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 214163 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 27812 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 12950 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1772414 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 18194678 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 86130501 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 21182613 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 5 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 16531195 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1663483 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 369349 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 301926 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2462039 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 3681622 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 3198899 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 554263 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 453752 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 17730825 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 507077 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 17704327 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 59995 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 1478553 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 3387139 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 37397 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 31276289 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.566062 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.918538 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 20752127 66.35% 66.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 5297030 16.94% 83.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3493708 11.17% 94.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1513821 4.84% 99.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 219597 0.70% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 31276289 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 1110256 27.87% 27.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 673 0.02% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1321373 33.17% 61.07% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1550767 38.93% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 10922763 61.70% 61.70% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 25931 0.15% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3184 0.02% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 3652522 20.63% 82.49% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 3099903 17.51% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 17704327 # Type of FU issued
system.cpu1.iq.rate 0.551661 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 3983069 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.224977 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 70728007 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 19724904 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 17354196 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 21687372 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 71019 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 284912 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 435 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 8471 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 200526 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 36020 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 53245 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 213403 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 522979 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 149253 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 18243784 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 3681622 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 3198899 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 268198 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 4775 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 139704 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 8471 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 19696 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 91512 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 111208 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 17534609 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 3585774 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 154586 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 5882 # number of nop insts executed
system.cpu1.iew.exec_refs 6645326 # number of memory reference insts executed
system.cpu1.iew.exec_branches 2522938 # Number of branches executed
system.cpu1.iew.exec_stores 3059552 # Number of stores executed
system.cpu1.iew.exec_rate 0.546373 # Inst execution rate
system.cpu1.iew.wb_sent 17440127 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 17354196 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 8664228 # num instructions producing a value
system.cpu1.iew.wb_consumers 13427268 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.540751 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.645271 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 1321053 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 469680 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 104293 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 30960244 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.541417 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.301399 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 22892252 73.94% 73.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 4806577 15.52% 89.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1404802 4.54% 94.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 524965 1.70% 95.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 440442 1.42% 97.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 285091 0.92% 98.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 183452 0.59% 98.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 97903 0.32% 98.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 324760 1.05% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 30960244 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 13688085 # Number of instructions committed
system.cpu1.commit.committedOps 16762412 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 6395083 # Number of memory references committed
system.cpu1.commit.loads 3396710 # Number of loads committed
system.cpu1.commit.membars 189727 # Number of memory barriers committed
system.cpu1.commit.branches 2413565 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 14968527 # Number of committed integer instructions.
system.cpu1.commit.function_calls 408976 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 10339164 61.68% 61.68% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 24981 0.15% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.83% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3184 0.02% 61.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.85% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 3396710 20.26% 82.11% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 2998373 17.89% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 16762412 # Class of committed instruction
system.cpu1.commit.bw_lim_events 324760 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 47828529 # The number of ROB reads
system.cpu1.rob.rob_writes 36474807 # The number of ROB writes
system.cpu1.timesIdled 47199 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 816455 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5622120065 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 13685021 # Number of Instructions Simulated
system.cpu1.committedOps 16759348 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.345100 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.345100 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.426421 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.426421 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 19625898 # number of integer regfile reads
system.cpu1.int_regfile_writes 11372751 # number of integer regfile writes
system.cpu1.cc_regfile_reads 63035720 # number of cc regfile reads
system.cpu1.cc_regfile_writes 5356524 # number of cc regfile writes
system.cpu1.misc_regfile_reads 45569068 # number of misc regfile reads
system.cpu1.misc_regfile_writes 348886 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 147018 # number of replacements
system.cpu1.dcache.tags.tagsinuse 469.878055 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 5728782 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 147355 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 38.877418 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 104643213000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.878055 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917731 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.917731 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 12638529 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 12638529 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 3017876 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3017876 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2482754 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 2482754 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41945 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 41945 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69025 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 69025 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61066 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 61066 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 5500630 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 5500630 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 5542575 # number of overall hits
system.cpu1.dcache.overall_hits::total 5542575 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 174243 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 174243 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 312530 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 312530 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23398 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 23398 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17766 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 17766 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23154 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23154 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 486773 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 486773 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 510171 # number of overall misses
system.cpu1.dcache.overall_misses::total 510171 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3329111500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3329111500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11702941948 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 11702941948 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 365873000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 365873000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 624012000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 624012000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1848000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1848000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 15032053448 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 15032053448 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 15032053448 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 15032053448 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3192119 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3192119 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2795284 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 2795284 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65343 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 65343 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86791 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 86791 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84220 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 84220 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 5987403 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 5987403 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 6052746 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 6052746 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054585 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.054585 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111806 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.111806 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358080 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358080 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.204699 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.204699 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274923 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274923 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081300 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.081300 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084288 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.084288 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 30881.033763 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 465 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1794947 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 35 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 29761 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.285714 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 60.312053 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 147018 # number of writebacks
system.cpu1.dcache.writebacks::total 147018 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 60609 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 60609 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 234531 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 234531 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12556 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12556 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 295140 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 295140 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 295140 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 295140 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113634 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 113634 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77999 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 77999 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22718 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 22718 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5210 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5210 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23154 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23154 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 191633 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 191633 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 214351 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 214351 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3075 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2419 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5494 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5494 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1698407500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1698407500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2883249956 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2883249956 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 419765000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 419765000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 102736000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 102736000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 600876000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 600876000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4581657456 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4581657456 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5001422456 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5001422456 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 438427500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 438427500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301840000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301840000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 740267500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 740267500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035598 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035598 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027904 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027904 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.347673 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.347673 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060029 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060029 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274923 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274923 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.032006 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035414 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035414 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36965.216939 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36965.216939 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.198697 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18477.198697 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19719.001919 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19719.001919 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25951.282716 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25951.282716 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23332.862716 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23332.862716 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142578.048780 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142578.048780 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124778.834229 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124778.834229 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134741.081179 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134741.081179 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 532644 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.385087 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 6412298 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 533156 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 12.027058 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 79429210500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.385087 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975361 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975361 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 14462114 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 14462114 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 6412298 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 6412298 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 6412298 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 6412298 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 6412298 # number of overall hits
system.cpu1.icache.overall_hits::total 6412298 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 552179 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 552179 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 552179 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 552179 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 552179 # number of overall misses
system.cpu1.icache.overall_misses::total 552179 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5065871620 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5065871620 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5065871620 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5065871620 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5065871620 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5065871620 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 6964477 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 6964477 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 6964477 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 6964477 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 6964477 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 6964477 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079285 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.079285 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079285 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.079285 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079285 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.079285 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9174.328651 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9174.328651 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9174.328651 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9174.328651 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 470749 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 422 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 34696 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.567818 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 105.500000 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 532644 # number of writebacks
system.cpu1.icache.writebacks::total 532644 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19019 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 19019 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 19019 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 19019 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 19019 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 19019 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 533160 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 533160 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 533160 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 533160 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 533160 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 533160 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4631400380 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4631400380 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4631400380 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4631400380 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4631400380 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4631400380 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13655000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13655000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13655000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 13655000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076554 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.076554 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.076554 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8686.698890 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133872.549020 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133872.549020 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 119604 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 120343 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 669 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 49745 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 36294 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15213.941609 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1184366 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 51460 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 23.015274 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14744.109202 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.751628 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 4.727886 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 454.352894 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.899909 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000656 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000289 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027731 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.928585 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 946 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14156 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 319 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 800 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2726 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10630 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057739 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864014 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 23534667 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 23534667 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 11642 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5450 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 17092 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 91128 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 91128 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 577481 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 577481 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16562 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 16562 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 522608 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 522608 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77065 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 77065 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 11642 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5450 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 522608 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 93627 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 633327 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 11642 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5450 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 522608 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 93627 # number of overall hits
system.cpu1.l2cache.overall_hits::total 633327 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 742 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29194 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29194 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23153 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23153 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32879 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 32879 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10546 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 10546 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64491 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 64491 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 10546 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 97370 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 108658 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 10546 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 97370 # number of overall misses
system.cpu1.l2cache.overall_misses::total 108658 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10388000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5548000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 15936000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 61302500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 61302500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 60199500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 60199500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1803000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1803000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1873781500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1873781500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 637936000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 637936000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1490442997 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1490442997 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10388000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5548000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 637936000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3364224497 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4018096497 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10388000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5548000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 637936000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3364224497 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4018096497 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12114 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 5720 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 17834 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91128 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 91128 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 577481 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 577481 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29194 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29194 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23153 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23153 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49441 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 49441 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 533154 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 533154 # number of ReadCleanReq accesses(hits+misses)
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system.cpu1.l2cache.overall_accesses::cpu1.inst 533154 # number of overall (read+write) accesses
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system.cpu1.l2cache.ReadReq_miss_rate::total 0.041606 # miss rate for ReadReq accesses
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system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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system.cpu1.l2cache.ReadExReq_miss_rate::total 0.665015 # miss rate for ReadExReq accesses
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system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019780 # miss rate for ReadCleanReq accesses
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system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047203 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019780 # miss rate for overall accesses
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system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20548.148148 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21477.088949 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2099.832157 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2099.832157 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2600.073425 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2600.073425 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1803000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1803000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56990.221722 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56990.221722 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60490.802200 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60490.802200 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23110.868137 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23110.868137 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
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system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34550.934549 # average overall miss latency
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system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu1.l2cache.writebacks::writebacks 29343 # number of writebacks
system.cpu1.l2cache.writebacks::total 29343 # number of writebacks
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system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
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system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 583735000 # number of UpgradeReq MSHR miss cycles
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1695000 # number of SCUpgradeFailReq MSHR miss cycles
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system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 574617500 # number of overall MSHR miss cycles
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system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 413788000 # number of ReadReq MSHR uncacheable cycles
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system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 283458994 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 283458994 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12890000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 697246994 # number of overall MSHR uncacheable cycles
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system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041606 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639328 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639328 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019775 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.455382 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.455382 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.144688 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173299 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15477.088949 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63888.870178 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19995.033226 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19995.033226 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18439.791776 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18439.791776 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1695000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1695000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50044.053909 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50044.053909 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54502.276392 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17100.912119 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17100.912119 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
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system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35980.867302 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134565.203252 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134302.171860 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117180.237288 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117180.237288 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126910.628686 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126900.820944 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests 1463686 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 739552 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 170999 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169235 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1764 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 24298 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 736701 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2419 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2419 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 121677 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 588534 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 90826 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 26224 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 69999 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41335 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 85194 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 56383 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 54101 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 533160 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 217797 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1599162 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 719912 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12717 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26238 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2358029 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 68212704 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24362994 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 22880 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48456 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 92647034 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 368307 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1093026 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.175061 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.384243 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 903444 82.66% 82.66% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 187818 17.18% 99.84% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 1764 0.16% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1093026 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1422321490 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 79991516 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 799908367 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 318043852 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 6997998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 14133980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
system.iobus.trans_dist::WriteReq 59424 # Transaction distribution
system.iobus.trans_dist::WriteResp 59424 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40405500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6085500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 34122000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187170938 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.550737 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256092273000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.550737 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909421 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909421 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32570877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32570877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4577184061 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4577184061 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32570877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32570877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32570877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32570877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129249.511905 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129249.511905 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129249.511905 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19970877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19970877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764245413 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2764245413 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 19970877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 19970877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 19970877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 19970877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79249.511905 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79249.511905 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76309.778407 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76309.778407 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 130481 # number of replacements
system.l2c.tags.tagsinuse 63162.524815 # Cycle average of tags in use
system.l2c.tags.total_refs 437656 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 194611 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.248876 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 13531.746388 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.289436 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065903 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8160.706658 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2775.310647 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33971.574296 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.602927 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909521 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1734.289932 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 612.780861 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2352.248246 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.206478 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000264 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.124523 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.042348 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.518365 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.026463 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009350 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035892 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.963784 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 30783 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 33327 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5989 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 24666 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4321 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 28334 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.469711 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.508530 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6042349 # Number of tag accesses
system.l2c.tags.data_accesses 6042349 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 262546 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 262546 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 32542 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 2076 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 34618 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2163 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 775 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2938 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3848 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1021 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 4869 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 186 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 34162 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 48429 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46477 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 7717 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 5261 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3686 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 146069 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 186 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 34162 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 52277 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 46477 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 7717 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 6282 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 3686 # number of demand (read+write) hits
system.l2c.demand_hits::total 150938 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 186 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits
system.l2c.overall_hits::cpu0.inst 34162 # number of overall hits
system.l2c.overall_hits::cpu0.data 52277 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 46477 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
system.l2c.overall_hits::cpu1.inst 7717 # number of overall hits
system.l2c.overall_hits::cpu1.data 6282 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 3686 # number of overall hits
system.l2c.overall_hits::total 150938 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 9567 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2216 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 11783 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 708 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11710 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8783 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 20493 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 19538 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9228 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134710 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2825 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 1059 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6993 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 174391 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 19538 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20938 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 134710 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9842 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6993 # number of demand (read+write) misses
system.l2c.demand_misses::total 194884 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 19538 # number of overall misses
system.l2c.overall_misses::cpu0.data 20938 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 134710 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2825 # number of overall misses
system.l2c.overall_misses::cpu1.data 9842 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6993 # number of overall misses
system.l2c.overall_misses::total 194884 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 21715500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 4407500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 26123000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5011500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2024500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 7036000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1773470500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1179481000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2952951500 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4090000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2590822501 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1287354500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 838000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 379417500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 152189500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 27002299072 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 4090000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 2590822501 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3060825000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 838000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 132500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 379417500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1331670500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 29955250572 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 4090000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 2590822501 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3060825000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 838000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 132500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 379417500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1331670500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of overall miss cycles
system.l2c.overall_miss_latency::total 29955250572 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 262546 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 262546 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 42109 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4292 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 46401 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2871 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2012 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 4883 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15558 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9804 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25362 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 214 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 99 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 53700 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 57657 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 181187 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 48 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 14 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 10542 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 6320 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10679 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 320460 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 214 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 99 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 53700 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 73215 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 181187 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 48 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 14 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 10542 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 16124 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10679 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 345822 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 214 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 99 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 53700 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 73215 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 181187 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 48 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 14 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 10542 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 16124 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10679 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 345822 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.227196 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.516309 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.253938 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.246604 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.614811 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.398321 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.752667 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.895859 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.808020 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.363836 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160050 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.071429 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.267976 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167563 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.544190 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.363836 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.285980 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.071429 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.267976 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.610394 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.563538 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.363836 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.285980 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.071429 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.267976 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.610394 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.563538 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2269.833804 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1988.944043 # average UpgradeReq miss latency
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system.l2c.overall_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for overall accesses
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 37993 # Transaction distribution
system.membus.trans_dist::ReadResp 212610 # Transaction distribution
system.membus.trans_dist::WriteReq 30918 # Transaction distribution
system.membus.trans_dist::WriteResp 30918 # Transaction distribution
system.membus.trans_dist::WritebackDirty 138325 # Transaction distribution
system.membus.trans_dist::CleanEvict 16163 # Transaction distribution
system.membus.trans_dist::UpgradeReq 72828 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40466 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 40267 # Transaction distribution
system.membus.trans_dist::ReadExResp 20420 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174618 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656523 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 778231 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 851180 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19049928 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 19240508 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21558652 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 119912 # Total snoops (count)
system.membus.snoop_fanout::samples 587818 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 587818 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 587818 # Request fanout histogram
system.membus.reqLayer0.occupancy 81915500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11626486 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1006913072 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1122228815 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1359881 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 988623 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 533441 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 142864 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 21333 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 20424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 909 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 37996 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 474339 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30918 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30918 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 400884 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 117322 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 107373 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 43404 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 150777 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50440 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50440 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 436359 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256848 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 266902 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1523750 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34918134 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4292486 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 39210620 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 443927 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 909712 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.336026 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.474459 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 604934 66.50% 66.50% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 303869 33.40% 99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 909 0.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 909712 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 874582688 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 652718656 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 208359113 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1876 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2727 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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