247e4e9ab4
Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated.
111 lines
12 KiB
Text
111 lines
12 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000052 # Number of seconds simulated
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sim_ticks 52498 # Number of ticks simulated
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final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 30872 # Simulator instruction rate (inst/s)
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host_op_rate 30864 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 628609 # Simulator tick rate (ticks/s)
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host_mem_usage 144188 # Number of bytes of host memory used
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host_seconds 0.08 # Real time elapsed on the host
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sim_insts 2577 # Number of instructions simulated
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sim_ops 2577 # Number of ops (including micro ops) simulated
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system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
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system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
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system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
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system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests
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system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads
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system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes
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system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
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system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue
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system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles
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system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request
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system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank
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system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus
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system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround
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system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration
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system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank
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system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 717 # DTB accesses
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system.cpu.itb.fetch_hits 2586 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2597 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 52498 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 2577 # Number of instructions committed
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system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
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system.cpu.num_func_calls 140 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
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system.cpu.num_int_insts 2375 # number of integer instructions
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system.cpu.num_fp_insts 6 # number of float instructions
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system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 717 # number of memory refs
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system.cpu.num_load_insts 419 # Number of load instructions
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system.cpu.num_store_insts 298 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 52498 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
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system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
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system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
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system.ruby.l1_cntrl0.Data 626 0.00% 0.00%
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system.ruby.l1_cntrl0.Replacement 622 0.00% 0.00%
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system.ruby.l1_cntrl0.Writeback_Ack 622 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Load 245 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Ifetch 297 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Store 84 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Load 170 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Ifetch 2288 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Store 210 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Replacement 622 0.00% 0.00%
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system.ruby.l1_cntrl0.MI.Writeback_Ack 622 0.00% 0.00%
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system.ruby.l1_cntrl0.IS.Data 542 0.00% 0.00%
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system.ruby.l1_cntrl0.IM.Data 84 0.00% 0.00%
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system.ruby.dir_cntrl0.GETX 626 0.00% 0.00%
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system.ruby.dir_cntrl0.PUTX 622 0.00% 0.00%
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system.ruby.dir_cntrl0.Memory_Data 626 0.00% 0.00%
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system.ruby.dir_cntrl0.Memory_Ack 622 0.00% 0.00%
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system.ruby.dir_cntrl0.I.GETX 626 0.00% 0.00%
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system.ruby.dir_cntrl0.M.PUTX 622 0.00% 0.00%
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system.ruby.dir_cntrl0.IM.Memory_Data 626 0.00% 0.00%
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system.ruby.dir_cntrl0.MI.Memory_Ack 622 0.00% 0.00%
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---------- End Simulation Statistics ----------
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