4ed184eade
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
551 lines
18 KiB
C++
551 lines
18 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_IEW_HH__
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#define __CPU_O3_IEW_HH__
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#include "config/full_system.hh"
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#include <queue>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/scoreboard.hh"
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#include "cpu/o3/lsq.hh"
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class FUPool;
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/**
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* DefaultIEW handles both single threaded and SMT IEW
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* (issue/execute/writeback). It handles the dispatching of
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* instructions to the LSQ/IQ as part of the issue stage, and has the
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* IQ try to issue instructions each cycle. The execute latency is
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* actually tied into the issue latency to allow the IQ to be able to
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* do back-to-back scheduling without having to speculatively schedule
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* instructions. This happens by having the IQ have access to the
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* functional units, and the IQ gets the execution latencies from the
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* FUs when it issues instructions. Instructions reach the execute
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* stage on the last cycle of their execution, which is when the IQ
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* knows to wake up any dependent instructions, allowing back to back
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* scheduling. The execute portion of IEW separates memory
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* instructions from non-memory instructions, either telling the LSQ
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* to execute the instruction, or executing the instruction directly.
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* The writeback portion of IEW completes the instructions by waking
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* up any dependents, and marking the register ready on the
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* scoreboard.
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*/
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template<class Impl>
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class DefaultIEW
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{
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private:
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//Typedefs from Impl
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::O3CPU O3CPU;
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typedef typename Impl::Params Params;
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typedef typename CPUPol::IQ IQ;
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typedef typename CPUPol::RenameMap RenameMap;
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typedef typename CPUPol::LSQ LSQ;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::IEWStruct IEWStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::IssueStruct IssueStruct;
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friend class Impl::O3CPU;
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friend class CPUPol::IQ;
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public:
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/** Overall IEW stage status. Used to determine if the CPU can
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* deschedule itself due to a lack of activity.
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*/
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enum Status {
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Active,
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Inactive
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};
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/** Status for Issue, Execute, and Writeback stages. */
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enum StageStatus {
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Running,
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Blocked,
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Idle,
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StartSquash,
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Squashing,
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Unblocking
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};
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private:
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/** Overall stage status. */
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Status _status;
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/** Dispatch status. */
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StageStatus dispatchStatus[Impl::MaxThreads];
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/** Execute status. */
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StageStatus exeStatus;
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/** Writeback status. */
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StageStatus wbStatus;
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public:
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/** Constructs a DefaultIEW with the given parameters. */
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DefaultIEW(Params *params);
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/** Returns the name of the DefaultIEW stage. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Initializes stage; sends back the number of free IQ and LSQ entries. */
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void initStage();
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/** Returns the dcache port. */
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Port *getDcachePort() { return ldstQueue.getDcachePort(); }
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/** Sets CPU pointer for IEW, IQ, and LSQ. */
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void setCPU(O3CPU *cpu_ptr);
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/** Sets main time buffer used for backwards communication. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Sets time buffer for getting instructions coming from rename. */
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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/** Sets time buffer to pass on instructions to commit. */
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<unsigned> *at_ptr);
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/** Sets pointer to the scoreboard. */
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void setScoreboard(Scoreboard *sb_ptr);
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/** Drains IEW stage. */
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bool drain();
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/** Resumes execution after a drain. */
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void resume();
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/** Completes switch out of IEW stage. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Returns if IEW is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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/** Squashes instructions in IEW for a specific thread. */
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void squash(unsigned tid);
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/** Wakes all dependents of a completed instruction. */
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void wakeDependents(DynInstPtr &inst);
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/** Tells memory dependence unit that a memory instruction needs to be
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* rescheduled. It will re-execute once replayMemInst() is called.
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*/
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void rescheduleMemInst(DynInstPtr &inst);
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/** Re-executes all rescheduled memory instructions. */
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void replayMemInst(DynInstPtr &inst);
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/** Sends an instruction to commit through the time buffer. */
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void instToCommit(DynInstPtr &inst);
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/** Inserts unused instructions of a thread into the skid buffer. */
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void skidInsert(unsigned tid);
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/** Returns the max of the number of entries in all of the skid buffers. */
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int skidCount();
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/** Returns if all of the skid buffers are empty. */
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bool skidsEmpty();
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/** Updates overall IEW status based on all of the stages' statuses. */
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void updateStatus();
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/** Resets entries of the IQ and the LSQ. */
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void resetEntries();
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/** Tells the CPU to wakeup if it has descheduled itself due to no
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* activity. Used mainly by the LdWritebackEvent.
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*/
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void wakeCPU();
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/** Reports to the CPU that there is activity this cycle. */
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void activityThisCycle();
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/** Tells CPU that the IEW stage is active and running. */
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inline void activateStage();
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/** Tells CPU that the IEW stage is inactive and idle. */
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inline void deactivateStage();
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/** Returns if the LSQ has any stores to writeback. */
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bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
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void incrWb(InstSeqNum &sn)
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{
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if (++wbOutstanding == wbMax)
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ableToIssue = false;
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DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
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assert(wbOutstanding <= wbMax);
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#ifdef DEBUG
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wbList.insert(sn);
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#endif
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}
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void decrWb(InstSeqNum &sn)
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{
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if (wbOutstanding-- == wbMax)
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ableToIssue = true;
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DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
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assert(wbOutstanding >= 0);
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#ifdef DEBUG
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assert(wbList.find(sn) != wbList.end());
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wbList.erase(sn);
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#endif
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}
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#ifdef DEBUG
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std::set<InstSeqNum> wbList;
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void dumpWb()
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{
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std::set<InstSeqNum>::iterator wb_it = wbList.begin();
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while (wb_it != wbList.end()) {
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cprintf("[sn:%lli]\n",
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(*wb_it));
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wb_it++;
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}
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}
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#endif
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bool canIssue() { return ableToIssue; }
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bool ableToIssue;
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private:
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/** Sends commit proper information for a squash due to a branch
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* mispredict.
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*/
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void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
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/** Sends commit proper information for a squash due to a memory order
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* violation.
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*/
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void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
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/** Sends commit proper information for a squash due to memory becoming
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* blocked (younger issued instructions must be retried).
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*/
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void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
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/** Sets Dispatch to blocked, and signals back to other stages to block. */
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void block(unsigned thread_id);
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/** Unblocks Dispatch if the skid buffer is empty, and signals back to
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* other stages to unblock.
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*/
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void unblock(unsigned thread_id);
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/** Determines proper actions to take given Dispatch's status. */
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void dispatch(unsigned tid);
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/** Dispatches instructions to IQ and LSQ. */
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void dispatchInsts(unsigned tid);
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/** Executes instructions. In the case of memory operations, it informs the
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* LSQ to execute the instructions. Also handles any redirects that occur
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* due to the executed instructions.
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*/
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void executeInsts();
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/** Writebacks instructions. In our model, the instruction's execute()
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* function atomically reads registers, executes, and writes registers.
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* Thus this writeback only wakes up dependent instructions, and informs
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* the scoreboard of registers becoming ready.
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*/
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void writebackInsts();
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/** Returns the number of valid, non-squashed instructions coming from
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* rename to dispatch.
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*/
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unsigned validInstsFromRename();
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/** Reads the stall signals. */
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void readStallSignals(unsigned tid);
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/** Checks if any of the stall conditions are currently true. */
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bool checkStall(unsigned tid);
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/** Processes inputs and changes state accordingly. */
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void checkSignalsAndUpdate(unsigned tid);
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/** Removes instructions from rename from a thread's instruction list. */
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void emptyRenameInsts(unsigned tid);
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/** Sorts instructions coming from rename into lists separated by thread. */
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void sortInsts();
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public:
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/** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
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* Writeback to run for one cycle.
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*/
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void tick();
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private:
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/** Updates execution stats based on the instruction. */
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void updateExeInstStats(DynInstPtr &inst);
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/** Pointer to main time buffer used for backwards communication. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toFetch;
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/** Wire to get commit's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toRename;
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/** Rename instruction queue interface. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to get rename's output from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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/** Issue stage queue. */
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TimeBuffer<IssueStruct> issueToExecQueue;
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/** Wire to read information from the issue stage time queue. */
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typename TimeBuffer<IssueStruct>::wire fromIssue;
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/**
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* IEW stage time buffer. Holds ROB indices of instructions that
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* can be marked as completed.
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*/
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to write infromation heading to commit. */
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typename TimeBuffer<IEWStruct>::wire toCommit;
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/** Queue of all instructions coming from rename this cycle. */
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std::queue<DynInstPtr> insts[Impl::MaxThreads];
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/** Skid buffer between rename and IEW. */
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std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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/** Scoreboard pointer. */
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Scoreboard* scoreboard;
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public:
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/** Instruction queue. */
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IQ instQueue;
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/** Load / store queue. */
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LSQ ldstQueue;
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/** Pointer to the functional unit pool. */
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FUPool *fuPool;
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private:
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/** CPU pointer. */
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O3CPU *cpu;
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/** Records if IEW has written to the time buffer this cycle, so that the
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* CPU can deschedule itself if there is no activity.
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*/
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bool wroteToTimeBuffer;
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/** Source of possible stalls. */
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struct Stalls {
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bool commit;
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};
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/** Stages that are telling IEW to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** Debug function to print instructions that are issued this cycle. */
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void printAvailableInsts();
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public:
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/** Records if the LSQ needs to be updated on the next cycle, so that
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* IEW knows if there will be activity on the next cycle.
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*/
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bool updateLSQNextCycle;
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private:
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/** Records if there is a fetch redirect on this cycle for each thread. */
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bool fetchRedirect[Impl::MaxThreads];
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/** Keeps track of the last valid branch delay slot instss for threads */
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InstSeqNum bdelayDoneSeqNum[Impl::MaxThreads];
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/** Used to track if all instructions have been dispatched this cycle.
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* If they have not, then blocking must have occurred, and the instructions
|
|
* would already be added to the skid buffer.
|
|
* @todo: Fix this hack.
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|
*/
|
|
bool dispatchedAllInsts;
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|
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/** Records if the queues have been changed (inserted or issued insts),
|
|
* so that IEW knows to broadcast the updated amount of free entries.
|
|
*/
|
|
bool updatedQueues;
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|
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/** Commit to IEW delay, in ticks. */
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unsigned commitToIEWDelay;
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/** Rename to IEW delay, in ticks. */
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unsigned renameToIEWDelay;
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|
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/**
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* Issue to execute delay, in ticks. What this actually represents is
|
|
* the amount of time it takes for an instruction to wake up, be
|
|
* scheduled, and sent to a FU for execution.
|
|
*/
|
|
unsigned issueToExecuteDelay;
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/** Width of dispatch, in instructions. */
|
|
unsigned dispatchWidth;
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|
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/** Width of issue, in instructions. */
|
|
unsigned issueWidth;
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|
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/** Index into queue of instructions being written back. */
|
|
unsigned wbNumInst;
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|
|
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/** Cycle number within the queue of instructions being written back.
|
|
* Used in case there are too many instructions writing back at the current
|
|
* cycle and writesbacks need to be scheduled for the future. See comments
|
|
* in instToCommit().
|
|
*/
|
|
unsigned wbCycle;
|
|
|
|
/** Number of instructions in flight that will writeback. */
|
|
|
|
/** Number of instructions in flight that will writeback. */
|
|
int wbOutstanding;
|
|
|
|
/** Writeback width. */
|
|
unsigned wbWidth;
|
|
|
|
/** Writeback width * writeback depth, where writeback depth is
|
|
* the number of cycles of writing back instructions that can be
|
|
* buffered. */
|
|
unsigned wbMax;
|
|
|
|
/** Number of active threads. */
|
|
unsigned numThreads;
|
|
|
|
/** Pointer to list of active threads. */
|
|
std::list<unsigned> *activeThreads;
|
|
|
|
/** Maximum size of the skid buffer. */
|
|
unsigned skidBufferMax;
|
|
|
|
/** Is this stage switched out. */
|
|
bool switchedOut;
|
|
|
|
/** Stat for total number of idle cycles. */
|
|
Stats::Scalar<> iewIdleCycles;
|
|
/** Stat for total number of squashing cycles. */
|
|
Stats::Scalar<> iewSquashCycles;
|
|
/** Stat for total number of blocking cycles. */
|
|
Stats::Scalar<> iewBlockCycles;
|
|
/** Stat for total number of unblocking cycles. */
|
|
Stats::Scalar<> iewUnblockCycles;
|
|
/** Stat for total number of instructions dispatched. */
|
|
Stats::Scalar<> iewDispatchedInsts;
|
|
/** Stat for total number of squashed instructions dispatch skips. */
|
|
Stats::Scalar<> iewDispSquashedInsts;
|
|
/** Stat for total number of dispatched load instructions. */
|
|
Stats::Scalar<> iewDispLoadInsts;
|
|
/** Stat for total number of dispatched store instructions. */
|
|
Stats::Scalar<> iewDispStoreInsts;
|
|
/** Stat for total number of dispatched non speculative instructions. */
|
|
Stats::Scalar<> iewDispNonSpecInsts;
|
|
/** Stat for number of times the IQ becomes full. */
|
|
Stats::Scalar<> iewIQFullEvents;
|
|
/** Stat for number of times the LSQ becomes full. */
|
|
Stats::Scalar<> iewLSQFullEvents;
|
|
/** Stat for total number of memory ordering violation events. */
|
|
Stats::Scalar<> memOrderViolationEvents;
|
|
/** Stat for total number of incorrect predicted taken branches. */
|
|
Stats::Scalar<> predictedTakenIncorrect;
|
|
/** Stat for total number of incorrect predicted not taken branches. */
|
|
Stats::Scalar<> predictedNotTakenIncorrect;
|
|
/** Stat for total number of mispredicted branches detected at execute. */
|
|
Stats::Formula branchMispredicts;
|
|
|
|
/** Stat for total number of executed instructions. */
|
|
Stats::Scalar<> iewExecutedInsts;
|
|
/** Stat for total number of executed load instructions. */
|
|
Stats::Vector<> iewExecLoadInsts;
|
|
/** Stat for total number of executed store instructions. */
|
|
// Stats::Scalar<> iewExecStoreInsts;
|
|
/** Stat for total number of squashed instructions skipped at execute. */
|
|
Stats::Scalar<> iewExecSquashedInsts;
|
|
/** Number of executed software prefetches. */
|
|
Stats::Vector<> iewExecutedSwp;
|
|
/** Number of executed nops. */
|
|
Stats::Vector<> iewExecutedNop;
|
|
/** Number of executed meomory references. */
|
|
Stats::Vector<> iewExecutedRefs;
|
|
/** Number of executed branches. */
|
|
Stats::Vector<> iewExecutedBranches;
|
|
/** Number of executed store instructions. */
|
|
Stats::Formula iewExecStoreInsts;
|
|
/** Number of instructions executed per cycle. */
|
|
Stats::Formula iewExecRate;
|
|
|
|
/** Number of instructions sent to commit. */
|
|
Stats::Vector<> iewInstsToCommit;
|
|
/** Number of instructions that writeback. */
|
|
Stats::Vector<> writebackCount;
|
|
/** Number of instructions that wake consumers. */
|
|
Stats::Vector<> producerInst;
|
|
/** Number of instructions that wake up from producers. */
|
|
Stats::Vector<> consumerInst;
|
|
/** Number of instructions that were delayed in writing back due
|
|
* to resource contention.
|
|
*/
|
|
Stats::Vector<> wbPenalized;
|
|
/** Number of instructions per cycle written back. */
|
|
Stats::Formula wbRate;
|
|
/** Average number of woken instructions per writeback. */
|
|
Stats::Formula wbFanout;
|
|
/** Number of instructions per cycle delayed in writing back . */
|
|
Stats::Formula wbPenalizedRate;
|
|
};
|
|
|
|
#endif // __CPU_O3_IEW_HH__
|