7f39291c81
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
Update refs for clock changes.
--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
416 lines
44 KiB
Text
416 lines
44 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 7744324 # Number of BTB hits
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global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted
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global.BPredUnit.lookups 15489897 # Number of BP lookups
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global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target.
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host_inst_rate 108228 # Simulator instruction rate (inst/s)
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host_mem_usage 159488 # Number of bytes of host memory used
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host_seconds 735.41 # Real time elapsed on the host
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host_tick_rate 23792996 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 79591756 # Number of instructions simulated
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sim_seconds 0.017498 # Number of seconds simulated
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sim_ticks 17497602000 # Number of ticks simulated
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system.cpu.commit.COM:branches 13754477 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 33996100
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 8358440 2458.65%
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1 8230566 2421.03%
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2 4712162 1386.09%
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3 3108634 914.41%
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4 2121957 624.18%
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5 1131901 332.95%
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6 1374606 404.34%
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7 697761 205.25%
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8 4260073 1253.11%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 88340672 # Number of instructions committed
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system.cpu.commit.COM:loads 20379399 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 35224018 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 79591756 # Number of Instructions Simulated
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system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
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system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 33236178 # number of overall hits
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system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 980372 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 201077 # number of replacements
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system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use
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system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 147781 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched
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system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 34995208
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system.cpu.fetch.rateDist.min_value 0
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0 16625619 4750.83%
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1 1365816 390.29%
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2 1258616 359.65%
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3 1410956 403.19%
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4 3900976 1114.72%
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5 1678758 479.71%
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6 612174 174.93%
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7 1011089 288.92%
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8 7131204 2037.77%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
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system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses
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system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 12690553 # number of overall hits
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system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses
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system.cpu.icache.overall_misses 87520 # number of overall misses
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|
system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.icache.replacements 84818 # number of replacements
|
|
system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 14304724 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 15116998 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 32801872 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
(null) 0 0.00% # Type of FU issued
|
|
IntAlu 46687810 55.95% # Type of FU issued
|
|
IntMult 45238 0.05% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 120004 0.14% # Type of FU issued
|
|
FloatCmp 87 0.00% # Type of FU issued
|
|
FloatCvt 122290 0.15% # Type of FU issued
|
|
FloatMult 50 0.00% # Type of FU issued
|
|
FloatDiv 37770 0.05% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 21206489 25.41% # Type of FU issued
|
|
MemWrite 15228353 18.25% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
IntAlu 169452 11.91% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 649726 45.68% # attempts to use FU when none available
|
|
MemWrite 603028 42.40% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 5876071 1679.11%
|
|
1 8518834 2434.29%
|
|
2 6419045 1834.26%
|
|
3 4436708 1267.80%
|
|
4 4423684 1264.08%
|
|
5 2554091 729.84%
|
|
6 1512126 432.10%
|
|
7 794096 226.92%
|
|
8 460553 131.60%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 269574 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 170199 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 136967 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 115938 # number of writebacks
|
|
system.cpu.numCycles 34995208 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|