7b40c36fbd
Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
27 lines
813 B
Plaintext
Executable file
27 lines
813 B
Plaintext
Executable file
M5 Simulator System
|
|
|
|
Copyright (c) 2001-2008
|
|
The Regents of The University of Michigan
|
|
All Rights Reserved
|
|
|
|
|
|
M5 compiled Apr 21 2009 18:04:32
|
|
M5 revision e6dd09514462 6117 default qtip tip stats-update
|
|
M5 started Apr 21 2009 18:05:08
|
|
M5 executing on zizzer
|
|
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
|
|
Global frequency set at 1000000000000 ticks per second
|
|
info: Entering event queue @ 0. Starting simulation...
|
|
Begining test of difficult SPARC instructions...
|
|
LDSTUB: Passed
|
|
SWAP: Passed
|
|
CAS FAIL: Passed
|
|
CAS WORK: Passed
|
|
CASX FAIL: Passed
|
|
CASX WORK: Passed
|
|
LDTX: Passed
|
|
LDTW: Passed
|
|
STTW: Passed
|
|
Done
|
|
Exiting @ tick 7618500 because target called exit()
|