2809 lines
352 KiB
Text
2809 lines
352 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.010000 # Number of seconds simulated
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sim_ticks 10000000000 # Number of ticks simulated
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final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_tick_rate 586000670 # Simulator tick rate (ticks/s)
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host_mem_usage 1428656 # Number of bytes of host memory used
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host_seconds 17.06 # Real time elapsed on the host
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::l0subsys0.tester0 2056192 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys0.tester1 2014720 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys1.tester0 2083456 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys1.tester1 2130880 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys2.tester0 2005568 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys2.tester1 2026048 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys3.tester0 2065280 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys3.tester1 2035584 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys4.tester0 2163904 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys4.tester1 2093312 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys5.tester0 2131712 # Number of bytes read from this memory
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system.physmem.bytes_read::l0subsys5.tester1 2070336 # Number of bytes read from this memory
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system.physmem.bytes_read::l2subsys0.tester 2185536 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27062528 # Number of bytes read from this memory
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system.physmem.bytes_written::writebacks 9533312 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9533312 # Number of bytes written to this memory
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system.physmem.num_reads::l0subsys0.tester0 32128 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys0.tester1 31480 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys1.tester0 32554 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys1.tester1 33295 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys2.tester0 31337 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys2.tester1 31657 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys3.tester0 32270 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys3.tester1 31806 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys4.tester0 33811 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys4.tester1 32708 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys5.tester0 33308 # Number of read requests responded to by this memory
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system.physmem.num_reads::l0subsys5.tester1 32349 # Number of read requests responded to by this memory
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system.physmem.num_reads::l2subsys0.tester 34149 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 422852 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 148958 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 148958 # Number of write requests responded to by this memory
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system.physmem.bw_read::l0subsys0.tester0 205619200 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys0.tester1 201472000 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys1.tester0 208345600 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys1.tester1 213088000 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys2.tester0 200556800 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys2.tester1 202604800 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys3.tester0 206528000 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys3.tester1 203558400 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys4.tester0 216390400 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys4.tester1 209331200 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys5.tester0 213171200 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l0subsys5.tester1 207033600 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::l2subsys0.tester 218553600 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2706252800 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 953331200 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 953331200 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 953331200 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys0.tester0 205619200 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys0.tester1 201472000 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys1.tester0 208345600 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys1.tester1 213088000 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys2.tester0 200556800 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys2.tester1 202604800 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys3.tester0 206528000 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys3.tester1 203558400 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys4.tester0 216390400 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys4.tester1 209331200 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys5.tester0 213171200 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l0subsys5.tester1 207033600 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::l2subsys0.tester 218553600 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3659584000 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 422854 # Number of read requests accepted
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system.physmem.writeReqs 148958 # Number of write requests accepted
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system.physmem.readBursts 422854 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 148958 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 27060224 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 2432 # Total number of bytes read from write queue
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system.physmem.bytesWritten 9531904 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 27062656 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 9533312 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 38 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 26538 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26515 # Per bank write bursts
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system.physmem.perBankRdBursts::2 26457 # Per bank write bursts
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system.physmem.perBankRdBursts::3 26413 # Per bank write bursts
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system.physmem.perBankRdBursts::4 26526 # Per bank write bursts
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system.physmem.perBankRdBursts::5 26432 # Per bank write bursts
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system.physmem.perBankRdBursts::6 26460 # Per bank write bursts
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system.physmem.perBankRdBursts::7 26446 # Per bank write bursts
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system.physmem.perBankRdBursts::8 26723 # Per bank write bursts
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system.physmem.perBankRdBursts::9 26408 # Per bank write bursts
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system.physmem.perBankRdBursts::10 26159 # Per bank write bursts
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system.physmem.perBankRdBursts::11 26321 # Per bank write bursts
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system.physmem.perBankRdBursts::12 26387 # Per bank write bursts
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system.physmem.perBankRdBursts::13 26566 # Per bank write bursts
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system.physmem.perBankRdBursts::14 26098 # Per bank write bursts
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system.physmem.perBankRdBursts::15 26367 # Per bank write bursts
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system.physmem.perBankWrBursts::0 9312 # Per bank write bursts
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system.physmem.perBankWrBursts::1 9367 # Per bank write bursts
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system.physmem.perBankWrBursts::2 9386 # Per bank write bursts
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system.physmem.perBankWrBursts::3 9443 # Per bank write bursts
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system.physmem.perBankWrBursts::4 9257 # Per bank write bursts
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system.physmem.perBankWrBursts::5 9263 # Per bank write bursts
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system.physmem.perBankWrBursts::6 9303 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9331 # Per bank write bursts
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system.physmem.perBankWrBursts::8 9435 # Per bank write bursts
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system.physmem.perBankWrBursts::9 9399 # Per bank write bursts
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system.physmem.perBankWrBursts::10 9280 # Per bank write bursts
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system.physmem.perBankWrBursts::11 9145 # Per bank write bursts
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system.physmem.perBankWrBursts::12 9382 # Per bank write bursts
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system.physmem.perBankWrBursts::13 9282 # Per bank write bursts
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system.physmem.perBankWrBursts::14 9214 # Per bank write bursts
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system.physmem.perBankWrBursts::15 9137 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 9999908219 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 422854 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 148958 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 43122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 85605 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 84278 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 61946 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 43434 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 30724 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 21728 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 15491 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 10921 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 7752 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 5579 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 3961 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 2651 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1810 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1278 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 839 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 584 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 407 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 282 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 163 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 99 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 60 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 46 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 32 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2139 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::18 4877 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::19 6843 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7878 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 8666 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 9331 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 9709 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::24 9888 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 10059 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::26 9944 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 10042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 10156 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 10189 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 10292 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 10096 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 9928 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1820 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1122 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::35 833 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 412 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 340 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 306 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 268 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 225 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 199 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 177 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 180 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 170 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 565061 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 64.756251 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 64.522780 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 7.121324 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::0-127 558476 98.83% 98.83% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::128-255 6582 1.16% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 1 0.00% 100.00% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::total 565061 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 9305 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 45.437292 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::gmean 43.280128 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 45.255047 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-255 9302 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::256-511 2 0.02% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::4096-4351 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 9305 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 9305 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.006018 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.005571 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 0.126830 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 9281 99.74% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 3 0.03% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 13 0.14% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 6 0.06% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 9305 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 23113331872 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 31041131872 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2114080000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 54665.23 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 73415.23 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2706.02 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 953.19 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2706.27 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 953.33 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 28.59 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 21.14 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 7.45 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 3.92 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 26.94 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 2662 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 4016 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 0.63 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 2.70 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 17488.10 # Average gap between requests
|
|
system.physmem.pageHitRate 1.17 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 2139737040 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 1167515250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1651455000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 483654240 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 6798762495 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 34896750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 12929011815 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 1293.176305 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 21746512 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 333840000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 9642298751 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 2131012800 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 1162755000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1645597200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 481140000 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 6796546335 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 36816750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 12906859125 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 1290.965729 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 25323820 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 333840000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 9638682193 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.tester0.numPackets 65034 # Number of packets generated
|
|
system.l0subsys0.tester0.numRetries 2631 # Number of retries
|
|
system.l0subsys0.tester0.retryTicks 64675381 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys0.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.tester1.numPackets 65594 # Number of packets generated
|
|
system.l0subsys0.tester1.numRetries 2683 # Number of retries
|
|
system.l0subsys0.tester1.retryTicks 67015418 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys0.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys0.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys0.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys0.xbar.trans_dist::ReadReq 84077 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::ReadResp 79156 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::WriteReq 46551 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::WriteResp 46551 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::WritebackDirty 22891 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::CleanEvict 74163 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::UpgradeReq 16582 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::ReadExReq 21053 # Transaction distribution
|
|
system.l0subsys0.xbar.trans_dist::ReadSharedReq 27577 # Transaction distribution
|
|
system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 130068 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 131188 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.pkt_count::total 261256 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 520272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 524752 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.pkt_size::total 1045024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys0.xbar.snoops 162266 # Total snoops (count)
|
|
system.l0subsys0.xbar.snoopTraffic 1465024 # Total snoop traffic (bytes)
|
|
system.l0subsys0.xbar.snoop_fanout::samples 295596 # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::0 295596 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys0.xbar.snoop_fanout::total 295596 # Request fanout histogram
|
|
system.l0subsys0.xbar.reqLayer0.occupancy 246613193 # Layer occupancy (ticks)
|
|
system.l0subsys0.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys0.xbar.respLayer0.occupancy 112497122 # Layer occupancy (ticks)
|
|
system.l0subsys0.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys0.xbar.respLayer1.occupancy 113637927 # Layer occupancy (ticks)
|
|
system.l0subsys0.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys1.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys1.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys1.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys1.tester0.numPackets 64234 # Number of packets generated
|
|
system.l0subsys1.tester0.numRetries 2842 # Number of retries
|
|
system.l0subsys1.tester0.retryTicks 72381522 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys1.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys1.tester1.numPackets 67237 # Number of packets generated
|
|
system.l0subsys1.tester1.numRetries 2791 # Number of retries
|
|
system.l0subsys1.tester1.retryTicks 70676938 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys1.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys1.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys1.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys1.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys1.xbar.trans_dist::ReadReq 84459 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::ReadResp 79428 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 5031 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::WriteReq 47012 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::WriteResp 47011 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::WritebackDirty 23704 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::CleanEvict 74816 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::UpgradeReq 15753 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::ReadExReq 20596 # Transaction distribution
|
|
system.l0subsys1.xbar.trans_dist::ReadSharedReq 26573 # Transaction distribution
|
|
system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 128468 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 134473 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.pkt_count::total 262941 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 513872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 537896 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.pkt_size::total 1051768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys1.xbar.snoops 161442 # Total snoops (count)
|
|
system.l0subsys1.xbar.snoopTraffic 1517056 # Total snoop traffic (bytes)
|
|
system.l0subsys1.xbar.snoop_fanout::samples 295865 # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::0 295865 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys1.xbar.snoop_fanout::total 295865 # Request fanout histogram
|
|
system.l0subsys1.xbar.reqLayer0.occupancy 248872620 # Layer occupancy (ticks)
|
|
system.l0subsys1.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys1.xbar.respLayer0.occupancy 110615455 # Layer occupancy (ticks)
|
|
system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys1.xbar.respLayer1.occupancy 116451863 # Layer occupancy (ticks)
|
|
system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%)
|
|
system.l0subsys2.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys2.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys2.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys2.tester0.numPackets 65812 # Number of packets generated
|
|
system.l0subsys2.tester0.numRetries 2732 # Number of retries
|
|
system.l0subsys2.tester0.retryTicks 67922794 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys2.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys2.tester1.numPackets 65437 # Number of packets generated
|
|
system.l0subsys2.tester1.numRetries 2695 # Number of retries
|
|
system.l0subsys2.tester1.retryTicks 66990492 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys2.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys2.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys2.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys2.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys2.xbar.trans_dist::ReadReq 84334 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::ReadResp 79404 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4929 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::WriteReq 46915 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::WriteResp 46915 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::WritebackDirty 22486 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::CleanEvict 73149 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::UpgradeReq 16126 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::ReadExReq 21115 # Transaction distribution
|
|
system.l0subsys2.xbar.trans_dist::ReadSharedReq 28234 # Transaction distribution
|
|
system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 131623 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 130874 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.pkt_count::total 262497 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 526488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 523496 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.pkt_size::total 1049984 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys2.xbar.snoops 161110 # Total snoops (count)
|
|
system.l0subsys2.xbar.snoopTraffic 1439104 # Total snoop traffic (bytes)
|
|
system.l0subsys2.xbar.snoop_fanout::samples 295231 # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::0 295231 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys2.xbar.snoop_fanout::total 295231 # Request fanout histogram
|
|
system.l0subsys2.xbar.reqLayer0.occupancy 248142071 # Layer occupancy (ticks)
|
|
system.l0subsys2.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys2.xbar.respLayer0.occupancy 114094156 # Layer occupancy (ticks)
|
|
system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys2.xbar.respLayer1.occupancy 113403149 # Layer occupancy (ticks)
|
|
system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys3.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys3.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys3.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys3.tester0.numPackets 65010 # Number of packets generated
|
|
system.l0subsys3.tester0.numRetries 2630 # Number of retries
|
|
system.l0subsys3.tester0.retryTicks 64351691 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys3.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys3.tester1.numPackets 65550 # Number of packets generated
|
|
system.l0subsys3.tester1.numRetries 2637 # Number of retries
|
|
system.l0subsys3.tester1.retryTicks 67267239 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys3.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys3.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys3.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys3.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys3.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys3.xbar.trans_dist::ReadReq 83832 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::ReadResp 78911 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::WriteReq 46728 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::WriteResp 46727 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::WritebackDirty 23115 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::CleanEvict 73076 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::UpgradeReq 16273 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::ReadExReq 21213 # Transaction distribution
|
|
system.l0subsys3.xbar.trans_dist::ReadSharedReq 27196 # Transaction distribution
|
|
system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 130019 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 131100 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.pkt_count::total 261119 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 520080 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 524400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.pkt_size::total 1044480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys3.xbar.snoops 160873 # Total snoops (count)
|
|
system.l0subsys3.xbar.snoopTraffic 1479360 # Total snoop traffic (bytes)
|
|
system.l0subsys3.xbar.snoop_fanout::samples 294076 # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::0 294076 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys3.xbar.snoop_fanout::total 294076 # Request fanout histogram
|
|
system.l0subsys3.xbar.reqLayer0.occupancy 246366404 # Layer occupancy (ticks)
|
|
system.l0subsys3.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys3.xbar.respLayer0.occupancy 112403324 # Layer occupancy (ticks)
|
|
system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys3.xbar.respLayer1.occupancy 113183873 # Layer occupancy (ticks)
|
|
system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys4.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys4.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys4.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys4.tester0.numPackets 66012 # Number of packets generated
|
|
system.l0subsys4.tester0.numRetries 2782 # Number of retries
|
|
system.l0subsys4.tester0.retryTicks 70240058 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys4.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys4.tester1.numPackets 66554 # Number of packets generated
|
|
system.l0subsys4.tester1.numRetries 2702 # Number of retries
|
|
system.l0subsys4.tester1.retryTicks 70715102 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys4.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys4.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys4.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys4.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys4.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys4.xbar.trans_dist::ReadReq 85335 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::ReadResp 80858 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4477 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::WriteReq 47231 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::WriteResp 47231 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::WritebackDirty 23610 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::CleanEvict 76410 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::UpgradeReq 15815 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::ReadExReq 19797 # Transaction distribution
|
|
system.l0subsys4.xbar.trans_dist::ReadSharedReq 26031 # Transaction distribution
|
|
system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 132024 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 133108 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.pkt_count::total 265132 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 528096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 532432 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.pkt_size::total 1060528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys4.xbar.snoops 161663 # Total snoops (count)
|
|
system.l0subsys4.xbar.snoopTraffic 1511040 # Total snoop traffic (bytes)
|
|
system.l0subsys4.xbar.snoop_fanout::samples 297063 # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::0 297063 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys4.xbar.snoop_fanout::total 297063 # Request fanout histogram
|
|
system.l0subsys4.xbar.reqLayer0.occupancy 250291221 # Layer occupancy (ticks)
|
|
system.l0subsys4.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys4.xbar.respLayer0.occupancy 115013486 # Layer occupancy (ticks)
|
|
system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.l0subsys4.xbar.respLayer1.occupancy 114676529 # Layer occupancy (ticks)
|
|
system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys5.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys5.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys5.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys5.tester0.numPackets 66218 # Number of packets generated
|
|
system.l0subsys5.tester0.numRetries 2474 # Number of retries
|
|
system.l0subsys5.tester0.retryTicks 63721903 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys5.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys5.tester1.numPackets 66053 # Number of packets generated
|
|
system.l0subsys5.tester1.numRetries 2552 # Number of retries
|
|
system.l0subsys5.tester1.retryTicks 62099800 # Time spent waiting due to back-pressure (ticks)
|
|
system.l0subsys5.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
|
system.l0subsys5.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys5.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys5.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l0subsys5.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l0subsys5.xbar.trans_dist::ReadReq 85318 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::ReadResp 80121 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 5196 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::WriteReq 46953 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::WriteResp 46953 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::WritebackDirty 23264 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::CleanEvict 76398 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::UpgradeReq 16610 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::ReadExReq 21094 # Transaction distribution
|
|
system.l0subsys5.xbar.trans_dist::ReadSharedReq 27416 # Transaction distribution
|
|
system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 132435 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 132106 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.pkt_count::total 264541 # Packet count per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 529736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 528424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.pkt_size::total 1058160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l0subsys5.xbar.snoops 164782 # Total snoops (count)
|
|
system.l0subsys5.xbar.snoopTraffic 1488896 # Total snoop traffic (bytes)
|
|
system.l0subsys5.xbar.snoop_fanout::samples 299602 # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::0 299602 100.00% 100.00% # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.l0subsys5.xbar.snoop_fanout::total 299602 # Request fanout histogram
|
|
system.l0subsys5.xbar.reqLayer0.occupancy 249141230 # Layer occupancy (ticks)
|
|
system.l0subsys5.xbar.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.l0subsys5.xbar.respLayer0.occupancy 114371637 # Layer occupancy (ticks)
|
|
system.l0subsys5.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.l0subsys5.xbar.respLayer1.occupancy 114160981 # Layer occupancy (ticks)
|
|
system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.l1subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys0.cache0.tags.replacements 63572 # number of replacements
|
|
system.l1subsys0.cache0.tags.tagsinuse 502.721619 # Cycle average of tags in use
|
|
system.l1subsys0.cache0.tags.total_refs 28948 # Total number of references to valid blocks.
|
|
system.l1subsys0.cache0.tags.sampled_refs 64070 # Sample count of references to valid blocks.
|
|
system.l1subsys0.cache0.tags.avg_refs 0.451818 # Average number of references to valid blocks.
|
|
system.l1subsys0.cache0.tags.warmup_cycle 175326000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester0 252.816838 # Average occupied blocks per requestor
|
|
system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester1 249.904781 # Average occupied blocks per requestor
|
|
system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester0 0.493783 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester1 0.488095 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache0.tags.occ_percent::total 0.981878 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache0.tags.occ_task_id_blocks::1024 498 # Occupied blocks per task id
|
|
system.l1subsys0.cache0.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
|
system.l1subsys0.cache0.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id
|
|
system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
|
|
system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.972656 # Percentage of cache occupancy per task id
|
|
system.l1subsys0.cache0.tags.tag_accesses 622356 # Number of tag accesses
|
|
system.l1subsys0.cache0.tags.data_accesses 622356 # Number of data accesses
|
|
system.l1subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9054 # number of ReadReq hits
|
|
system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9218 # number of ReadReq hits
|
|
system.l1subsys0.cache0.ReadReq_hits::total 18272 # number of ReadReq hits
|
|
system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester0 1043 # number of WriteReq hits
|
|
system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester1 1065 # number of WriteReq hits
|
|
system.l1subsys0.cache0.WriteReq_hits::total 2108 # number of WriteReq hits
|
|
system.l1subsys0.cache0.demand_hits::l0subsys0.tester0 10097 # number of demand (read+write) hits
|
|
system.l1subsys0.cache0.demand_hits::l0subsys0.tester1 10283 # number of demand (read+write) hits
|
|
system.l1subsys0.cache0.demand_hits::total 20380 # number of demand (read+write) hits
|
|
system.l1subsys0.cache0.overall_hits::l0subsys0.tester0 10097 # number of overall hits
|
|
system.l1subsys0.cache0.overall_hits::l0subsys0.tester1 10283 # number of overall hits
|
|
system.l1subsys0.cache0.overall_hits::total 20380 # number of overall hits
|
|
system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester0 32756 # number of ReadReq misses
|
|
system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester1 33049 # number of ReadReq misses
|
|
system.l1subsys0.cache0.ReadReq_misses::total 65805 # number of ReadReq misses
|
|
system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester0 22181 # number of WriteReq misses
|
|
system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester1 22262 # number of WriteReq misses
|
|
system.l1subsys0.cache0.WriteReq_misses::total 44443 # number of WriteReq misses
|
|
system.l1subsys0.cache0.demand_misses::l0subsys0.tester0 54937 # number of demand (read+write) misses
|
|
system.l1subsys0.cache0.demand_misses::l0subsys0.tester1 55311 # number of demand (read+write) misses
|
|
system.l1subsys0.cache0.demand_misses::total 110248 # number of demand (read+write) misses
|
|
system.l1subsys0.cache0.overall_misses::l0subsys0.tester0 54937 # number of overall misses
|
|
system.l1subsys0.cache0.overall_misses::l0subsys0.tester1 55311 # number of overall misses
|
|
system.l1subsys0.cache0.overall_misses::total 110248 # number of overall misses
|
|
system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester0 3001619678 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester1 2958296743 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache0.ReadReq_miss_latency::total 5959916421 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester0 1842729426 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester1 1811086120 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache0.WriteReq_miss_latency::total 3653815546 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester0 4844349104 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester1 4769382863 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache0.demand_miss_latency::total 9613731967 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester0 4844349104 # number of overall miss cycles
|
|
system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester1 4769382863 # number of overall miss cycles
|
|
system.l1subsys0.cache0.overall_miss_latency::total 9613731967 # number of overall miss cycles
|
|
system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester0 41810 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester1 42267 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.ReadReq_accesses::total 84077 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester0 23224 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester1 23327 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.WriteReq_accesses::total 46551 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache0.demand_accesses::l0subsys0.tester0 65034 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache0.demand_accesses::l0subsys0.tester1 65594 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache0.demand_accesses::total 130628 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache0.overall_accesses::l0subsys0.tester0 65034 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache0.overall_accesses::l0subsys0.tester1 65594 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache0.overall_accesses::total 130628 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester0 0.783449 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester1 0.781910 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.ReadReq_miss_rate::total 0.782675 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester0 0.955090 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester1 0.954345 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.WriteReq_miss_rate::total 0.954716 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester0 0.844743 # miss rate for demand accesses
|
|
system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester1 0.843233 # miss rate for demand accesses
|
|
system.l1subsys0.cache0.demand_miss_rate::total 0.843984 # miss rate for demand accesses
|
|
system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester0 0.844743 # miss rate for overall accesses
|
|
system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester1 0.843233 # miss rate for overall accesses
|
|
system.l1subsys0.cache0.overall_miss_rate::total 0.843984 # miss rate for overall accesses
|
|
system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester0 91635.721028 # average ReadReq miss latency
|
|
system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester1 89512.443432 # average ReadReq miss latency
|
|
system.l1subsys0.cache0.ReadReq_avg_miss_latency::total 90569.355231 # average ReadReq miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester0 83076.931879 # average WriteReq miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester1 81353.253077 # average WriteReq miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_miss_latency::total 82213.521724 # average WriteReq miss latency
|
|
system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency
|
|
system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency
|
|
system.l1subsys0.cache0.demand_avg_miss_latency::total 87200.964798 # average overall miss latency
|
|
system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency
|
|
system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency
|
|
system.l1subsys0.cache0.overall_avg_miss_latency::total 87200.964798 # average overall miss latency
|
|
system.l1subsys0.cache0.blocked_cycles::no_mshrs 255047 # number of cycles access was blocked
|
|
system.l1subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys0.cache0.blocked::no_mshrs 7903 # number of cycles access was blocked
|
|
system.l1subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys0.cache0.avg_blocked_cycles::no_mshrs 32.272175 # average number of cycles each access was blocked
|
|
system.l1subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys0.cache0.writebacks::writebacks 22887 # number of writebacks
|
|
system.l1subsys0.cache0.writebacks::total 22887 # number of writebacks
|
|
system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester0 1216 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester1 1243 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache0.ReadReq_mshr_hits::total 2459 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester0 661 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester1 689 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache0.WriteReq_mshr_hits::total 1350 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester0 1877 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester1 1932 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache0.demand_mshr_hits::total 3809 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester0 1877 # number of overall MSHR hits
|
|
system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester1 1932 # number of overall MSHR hits
|
|
system.l1subsys0.cache0.overall_mshr_hits::total 3809 # number of overall MSHR hits
|
|
system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester0 31540 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester1 31806 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache0.ReadReq_mshr_misses::total 63346 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester0 21520 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester1 21573 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache0.WriteReq_mshr_misses::total 43093 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester0 53060 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester1 53379 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache0.demand_mshr_misses::total 106439 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester0 53060 # number of overall MSHR misses
|
|
system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester1 53379 # number of overall MSHR misses
|
|
system.l1subsys0.cache0.overall_mshr_misses::total 106439 # number of overall MSHR misses
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester0 2943016198 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester1 2898664159 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_latency::total 5841680357 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester0 1812017394 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester1 1780656760 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_latency::total 3592674154 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache0.demand_mshr_miss_latency::total 9434354511 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache0.overall_mshr_miss_latency::total 9434354511 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester0 0.754365 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester1 0.752502 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.ReadReq_mshr_miss_rate::total 0.753428 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester0 0.926628 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester1 0.924808 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.WriteReq_mshr_miss_rate::total 0.925716 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache0.demand_mshr_miss_rate::total 0.814825 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache0.overall_mshr_miss_rate::total 0.814825 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester0 93310.596005 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester1 91135.765547 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 92218.614546 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester0 84201.551766 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester1 82540.989199 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 83370.249321 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency
|
|
system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency
|
|
system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency
|
|
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency
|
|
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency
|
|
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys0.cache1.tags.replacements 65828 # number of replacements
|
|
system.l1subsys0.cache1.tags.tagsinuse 503.967314 # Cycle average of tags in use
|
|
system.l1subsys0.cache1.tags.total_refs 28277 # Total number of references to valid blocks.
|
|
system.l1subsys0.cache1.tags.sampled_refs 66340 # Sample count of references to valid blocks.
|
|
system.l1subsys0.cache1.tags.avg_refs 0.426244 # Average number of references to valid blocks.
|
|
system.l1subsys0.cache1.tags.warmup_cycle 396891000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 249.180331 # Average occupied blocks per requestor
|
|
system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 254.786982 # Average occupied blocks per requestor
|
|
system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.486680 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.497631 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache1.tags.occ_percent::total 0.984311 # Average percentage of cache occupancy
|
|
system.l1subsys0.cache1.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.l1subsys0.cache1.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
|
system.l1subsys0.cache1.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
|
|
system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
|
|
system.l1subsys0.cache1.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.l1subsys0.cache1.tags.tag_accesses 626837 # Number of tag accesses
|
|
system.l1subsys0.cache1.tags.data_accesses 626837 # Number of data accesses
|
|
system.l1subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 8196 # number of ReadReq hits
|
|
system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester1 9493 # number of ReadReq hits
|
|
system.l1subsys0.cache1.ReadReq_hits::total 17689 # number of ReadReq hits
|
|
system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester0 993 # number of WriteReq hits
|
|
system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester1 1169 # number of WriteReq hits
|
|
system.l1subsys0.cache1.WriteReq_hits::total 2162 # number of WriteReq hits
|
|
system.l1subsys0.cache1.demand_hits::l0subsys1.tester0 9189 # number of demand (read+write) hits
|
|
system.l1subsys0.cache1.demand_hits::l0subsys1.tester1 10662 # number of demand (read+write) hits
|
|
system.l1subsys0.cache1.demand_hits::total 19851 # number of demand (read+write) hits
|
|
system.l1subsys0.cache1.overall_hits::l0subsys1.tester0 9189 # number of overall hits
|
|
system.l1subsys0.cache1.overall_hits::l0subsys1.tester1 10662 # number of overall hits
|
|
system.l1subsys0.cache1.overall_hits::total 19851 # number of overall hits
|
|
system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester0 32989 # number of ReadReq misses
|
|
system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester1 33781 # number of ReadReq misses
|
|
system.l1subsys0.cache1.ReadReq_misses::total 66770 # number of ReadReq misses
|
|
system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester0 22056 # number of WriteReq misses
|
|
system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester1 22794 # number of WriteReq misses
|
|
system.l1subsys0.cache1.WriteReq_misses::total 44850 # number of WriteReq misses
|
|
system.l1subsys0.cache1.demand_misses::l0subsys1.tester0 55045 # number of demand (read+write) misses
|
|
system.l1subsys0.cache1.demand_misses::l0subsys1.tester1 56575 # number of demand (read+write) misses
|
|
system.l1subsys0.cache1.demand_misses::total 111620 # number of demand (read+write) misses
|
|
system.l1subsys0.cache1.overall_misses::l0subsys1.tester0 55045 # number of overall misses
|
|
system.l1subsys0.cache1.overall_misses::l0subsys1.tester1 56575 # number of overall misses
|
|
system.l1subsys0.cache1.overall_misses::total 111620 # number of overall misses
|
|
system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester0 2994338952 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester1 3071169807 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache1.ReadReq_miss_latency::total 6065508759 # number of ReadReq miss cycles
|
|
system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester0 1858284940 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester1 1885823655 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache1.WriteReq_miss_latency::total 3744108595 # number of WriteReq miss cycles
|
|
system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4852623892 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4956993462 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache1.demand_miss_latency::total 9809617354 # number of demand (read+write) miss cycles
|
|
system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4852623892 # number of overall miss cycles
|
|
system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4956993462 # number of overall miss cycles
|
|
system.l1subsys0.cache1.overall_miss_latency::total 9809617354 # number of overall miss cycles
|
|
system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester0 41185 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester1 43274 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.ReadReq_accesses::total 84459 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester0 23049 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester1 23963 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.WriteReq_accesses::total 47012 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys0.cache1.demand_accesses::l0subsys1.tester0 64234 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache1.demand_accesses::l0subsys1.tester1 67237 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache1.demand_accesses::total 131471 # number of demand (read+write) accesses
|
|
system.l1subsys0.cache1.overall_accesses::l0subsys1.tester0 64234 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache1.overall_accesses::l0subsys1.tester1 67237 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache1.overall_accesses::total 131471 # number of overall (read+write) accesses
|
|
system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester0 0.800996 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester1 0.780630 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.ReadReq_miss_rate::total 0.790561 # miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester0 0.956918 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester1 0.951216 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.WriteReq_miss_rate::total 0.954012 # miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.856945 # miss rate for demand accesses
|
|
system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.841427 # miss rate for demand accesses
|
|
system.l1subsys0.cache1.demand_miss_rate::total 0.849009 # miss rate for demand accesses
|
|
system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.856945 # miss rate for overall accesses
|
|
system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.841427 # miss rate for overall accesses
|
|
system.l1subsys0.cache1.overall_miss_rate::total 0.849009 # miss rate for overall accesses
|
|
system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester0 90767.799933 # average ReadReq miss latency
|
|
system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester1 90914.117610 # average ReadReq miss latency
|
|
system.l1subsys0.cache1.ReadReq_avg_miss_latency::total 90841.826554 # average ReadReq miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester0 84253.035002 # average WriteReq miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester1 82733.335746 # average WriteReq miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_miss_latency::total 83480.682163 # average WriteReq miss latency
|
|
system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 88157.396530 # average overall miss latency
|
|
system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 87618.090358 # average overall miss latency
|
|
system.l1subsys0.cache1.demand_avg_miss_latency::total 87884.047250 # average overall miss latency
|
|
system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 88157.396530 # average overall miss latency
|
|
system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 87618.090358 # average overall miss latency
|
|
system.l1subsys0.cache1.overall_avg_miss_latency::total 87884.047250 # average overall miss latency
|
|
system.l1subsys0.cache1.blocked_cycles::no_mshrs 279679 # number of cycles access was blocked
|
|
system.l1subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys0.cache1.blocked::no_mshrs 8747 # number of cycles access was blocked
|
|
system.l1subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys0.cache1.avg_blocked_cycles::no_mshrs 31.974277 # average number of cycles each access was blocked
|
|
system.l1subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys0.cache1.writebacks::writebacks 23700 # number of writebacks
|
|
system.l1subsys0.cache1.writebacks::total 23700 # number of writebacks
|
|
system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester0 1375 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester1 1361 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache1.ReadReq_mshr_hits::total 2736 # number of ReadReq MSHR hits
|
|
system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester0 770 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester1 782 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache1.WriteReq_mshr_hits::total 1552 # number of WriteReq MSHR hits
|
|
system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 2145 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 2143 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache1.demand_mshr_hits::total 4288 # number of demand (read+write) MSHR hits
|
|
system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 2145 # number of overall MSHR hits
|
|
system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 2143 # number of overall MSHR hits
|
|
system.l1subsys0.cache1.overall_mshr_hits::total 4288 # number of overall MSHR hits
|
|
system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester0 31614 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester1 32420 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache1.ReadReq_mshr_misses::total 64034 # number of ReadReq MSHR misses
|
|
system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester0 21286 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester1 22012 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache1.WriteReq_mshr_misses::total 43298 # number of WriteReq MSHR misses
|
|
system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 52900 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 54432 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache1.demand_mshr_misses::total 107332 # number of demand (read+write) MSHR misses
|
|
system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 52900 # number of overall MSHR misses
|
|
system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 54432 # number of overall MSHR misses
|
|
system.l1subsys0.cache1.overall_mshr_misses::total 107332 # number of overall MSHR misses
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester0 2931797311 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester1 3008653517 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_latency::total 5940450828 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester0 1826715134 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester1 1854734052 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_latency::total 3681449186 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache1.demand_mshr_miss_latency::total 9621900014 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache1.overall_mshr_miss_latency::total 9621900014 # number of overall MSHR miss cycles
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester0 0.767610 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester1 0.749180 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.ReadReq_mshr_miss_rate::total 0.758167 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester0 0.923511 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester1 0.918583 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.WriteReq_mshr_miss_rate::total 0.920999 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache1.demand_mshr_miss_rate::total 0.816393 # mshr miss rate for demand accesses
|
|
system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache1.overall_mshr_miss_rate::total 0.816393 # mshr miss rate for overall accesses
|
|
system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester0 92737.309768 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester1 92802.391024 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::total 92770.259987 # average ReadReq mshr miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester0 85817.679883 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester1 84260.133200 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::total 85025.848446 # average WriteReq mshr miss latency
|
|
system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.demand_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency
|
|
system.l1subsys0.cache1.overall_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency
|
|
system.l1subsys0.xbar.snoop_filter.tot_requests 345070 # Total number of requests made to the snoop filter.
|
|
system.l1subsys0.xbar.snoop_filter.hit_single_requests 163003 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8917 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys0.xbar.snoop_filter.tot_snoops 156506 # Total number of snoops made to the snoop filter.
|
|
system.l1subsys0.xbar.snoop_filter.hit_single_snoops 138247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 18259 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys0.xbar.trans_dist::ReadResp 154272 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 4493 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::WritebackDirty 92411 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::CleanEvict 188842 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::UpgradeReq 38589 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::UpgradeResp 23198 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::ReadExReq 102825 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::ReadExResp 93371 # Transaction distribution
|
|
system.l1subsys0.xbar.trans_dist::ReadSharedReq 169934 # Transaction distribution
|
|
system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 301161 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 304465 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.pkt_count::total 605626 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 9099264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 9173504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.pkt_size::total 18272768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys0.xbar.snoops 321974 # Total snoops (count)
|
|
system.l1subsys0.xbar.snoopTraffic 7063936 # Total snoop traffic (bytes)
|
|
system.l1subsys0.xbar.snoop_fanout::samples 463201 # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::mean 0.438401 # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::stdev 0.570127 # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::0 278392 60.10% 60.10% # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::1 166550 35.96% 96.06% # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::2 18259 3.94% 100.00% # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.l1subsys0.xbar.snoop_fanout::total 463201 # Request fanout histogram
|
|
system.l1subsys0.xbar.reqLayer0.occupancy 536944163 # Layer occupancy (ticks)
|
|
system.l1subsys0.xbar.reqLayer0.utilization 5.4 # Layer utilization (%)
|
|
system.l1subsys0.xbar.snoopLayer0.occupancy 181542409 # Layer occupancy (ticks)
|
|
system.l1subsys0.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
|
|
system.l1subsys0.xbar.respLayer0.occupancy 313026103 # Layer occupancy (ticks)
|
|
system.l1subsys0.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
|
|
system.l1subsys0.xbar.respLayer1.occupancy 316235883 # Layer occupancy (ticks)
|
|
system.l1subsys0.xbar.respLayer1.utilization 3.2 # Layer utilization (%)
|
|
system.l1subsys1.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys1.cache0.tags.replacements 62894 # number of replacements
|
|
system.l1subsys1.cache0.tags.tagsinuse 502.360512 # Cycle average of tags in use
|
|
system.l1subsys1.cache0.tags.total_refs 30318 # Total number of references to valid blocks.
|
|
system.l1subsys1.cache0.tags.sampled_refs 63398 # Sample count of references to valid blocks.
|
|
system.l1subsys1.cache0.tags.avg_refs 0.478217 # Average number of references to valid blocks.
|
|
system.l1subsys1.cache0.tags.warmup_cycle 195013000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester0 249.855893 # Average occupied blocks per requestor
|
|
system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester1 252.504619 # Average occupied blocks per requestor
|
|
system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester0 0.488000 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester1 0.493173 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache0.tags.occ_percent::total 0.981173 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
|
|
system.l1subsys1.cache0.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
|
system.l1subsys1.cache0.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id
|
|
system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
|
|
system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
|
|
system.l1subsys1.cache0.tags.tag_accesses 623844 # Number of tag accesses
|
|
system.l1subsys1.cache0.tags.data_accesses 623844 # Number of data accesses
|
|
system.l1subsys1.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 9625 # number of ReadReq hits
|
|
system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9444 # number of ReadReq hits
|
|
system.l1subsys1.cache0.ReadReq_hits::total 19069 # number of ReadReq hits
|
|
system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester0 1133 # number of WriteReq hits
|
|
system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester1 1194 # number of WriteReq hits
|
|
system.l1subsys1.cache0.WriteReq_hits::total 2327 # number of WriteReq hits
|
|
system.l1subsys1.cache0.demand_hits::l0subsys2.tester0 10758 # number of demand (read+write) hits
|
|
system.l1subsys1.cache0.demand_hits::l0subsys2.tester1 10638 # number of demand (read+write) hits
|
|
system.l1subsys1.cache0.demand_hits::total 21396 # number of demand (read+write) hits
|
|
system.l1subsys1.cache0.overall_hits::l0subsys2.tester0 10758 # number of overall hits
|
|
system.l1subsys1.cache0.overall_hits::l0subsys2.tester1 10638 # number of overall hits
|
|
system.l1subsys1.cache0.overall_hits::total 21396 # number of overall hits
|
|
system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester0 32686 # number of ReadReq misses
|
|
system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester1 32579 # number of ReadReq misses
|
|
system.l1subsys1.cache0.ReadReq_misses::total 65265 # number of ReadReq misses
|
|
system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester0 22368 # number of WriteReq misses
|
|
system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester1 22220 # number of WriteReq misses
|
|
system.l1subsys1.cache0.WriteReq_misses::total 44588 # number of WriteReq misses
|
|
system.l1subsys1.cache0.demand_misses::l0subsys2.tester0 55054 # number of demand (read+write) misses
|
|
system.l1subsys1.cache0.demand_misses::l0subsys2.tester1 54799 # number of demand (read+write) misses
|
|
system.l1subsys1.cache0.demand_misses::total 109853 # number of demand (read+write) misses
|
|
system.l1subsys1.cache0.overall_misses::l0subsys2.tester0 55054 # number of overall misses
|
|
system.l1subsys1.cache0.overall_misses::l0subsys2.tester1 54799 # number of overall misses
|
|
system.l1subsys1.cache0.overall_misses::total 109853 # number of overall misses
|
|
system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester0 2952180938 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester1 2978156965 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache0.ReadReq_miss_latency::total 5930337903 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester0 1826783335 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester1 1815663793 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache0.WriteReq_miss_latency::total 3642447128 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester0 4778964273 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester1 4793820758 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache0.demand_miss_latency::total 9572785031 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester0 4778964273 # number of overall miss cycles
|
|
system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester1 4793820758 # number of overall miss cycles
|
|
system.l1subsys1.cache0.overall_miss_latency::total 9572785031 # number of overall miss cycles
|
|
system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester0 42311 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester1 42023 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.ReadReq_accesses::total 84334 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester0 23501 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester1 23414 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.WriteReq_accesses::total 46915 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache0.demand_accesses::l0subsys2.tester0 65812 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache0.demand_accesses::l0subsys2.tester1 65437 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache0.demand_accesses::total 131249 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache0.overall_accesses::l0subsys2.tester0 65812 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache0.overall_accesses::l0subsys2.tester1 65437 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache0.overall_accesses::total 131249 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester0 0.772518 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester1 0.775266 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.ReadReq_miss_rate::total 0.773887 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester0 0.951789 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester1 0.949005 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.WriteReq_miss_rate::total 0.950400 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester0 0.836534 # miss rate for demand accesses
|
|
system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester1 0.837431 # miss rate for demand accesses
|
|
system.l1subsys1.cache0.demand_miss_rate::total 0.836982 # miss rate for demand accesses
|
|
system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester0 0.836534 # miss rate for overall accesses
|
|
system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester1 0.837431 # miss rate for overall accesses
|
|
system.l1subsys1.cache0.overall_miss_rate::total 0.836982 # miss rate for overall accesses
|
|
system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester0 90319.431500 # average ReadReq miss latency
|
|
system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester1 91413.394058 # average ReadReq miss latency
|
|
system.l1subsys1.cache0.ReadReq_avg_miss_latency::total 90865.516019 # average ReadReq miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester0 81669.498167 # average WriteReq miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester1 81713.041989 # average WriteReq miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_miss_latency::total 81691.197811 # average WriteReq miss latency
|
|
system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency
|
|
system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency
|
|
system.l1subsys1.cache0.demand_avg_miss_latency::total 87141.771558 # average overall miss latency
|
|
system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency
|
|
system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency
|
|
system.l1subsys1.cache0.overall_avg_miss_latency::total 87141.771558 # average overall miss latency
|
|
system.l1subsys1.cache0.blocked_cycles::no_mshrs 273729 # number of cycles access was blocked
|
|
system.l1subsys1.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys1.cache0.blocked::no_mshrs 8512 # number of cycles access was blocked
|
|
system.l1subsys1.cache0.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys1.cache0.avg_blocked_cycles::no_mshrs 32.158012 # average number of cycles each access was blocked
|
|
system.l1subsys1.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys1.cache0.writebacks::writebacks 22484 # number of writebacks
|
|
system.l1subsys1.cache0.writebacks::total 22484 # number of writebacks
|
|
system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester0 1351 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester1 1340 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache0.ReadReq_mshr_hits::total 2691 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester0 761 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester1 811 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache0.WriteReq_mshr_hits::total 1572 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester0 2112 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester1 2151 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache0.demand_mshr_hits::total 4263 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester0 2112 # number of overall MSHR hits
|
|
system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester1 2151 # number of overall MSHR hits
|
|
system.l1subsys1.cache0.overall_mshr_hits::total 4263 # number of overall MSHR hits
|
|
system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester0 31335 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester1 31239 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache0.ReadReq_mshr_misses::total 62574 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester0 21607 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester1 21409 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache0.WriteReq_mshr_misses::total 43016 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester0 52942 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester1 52648 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache0.demand_mshr_misses::total 105590 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester0 52942 # number of overall MSHR misses
|
|
system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester1 52648 # number of overall MSHR misses
|
|
system.l1subsys1.cache0.overall_mshr_misses::total 105590 # number of overall MSHR misses
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester0 2891074988 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester1 2917502752 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_latency::total 5808577740 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester0 1795222958 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester1 1782842702 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_latency::total 3578065660 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache0.demand_mshr_miss_latency::total 9386643400 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache0.overall_mshr_miss_latency::total 9386643400 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester0 0.740588 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester1 0.743379 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.ReadReq_mshr_miss_rate::total 0.741978 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester0 0.919408 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester1 0.914367 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.WriteReq_mshr_miss_rate::total 0.916892 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache0.demand_mshr_miss_rate::total 0.804501 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache0.overall_mshr_miss_rate::total 0.804501 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester0 92263.443051 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester1 93392.962387 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::total 92827.336274 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester0 83085.248207 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester1 83275.384278 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::total 83179.878650 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency
|
|
system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency
|
|
system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency
|
|
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency
|
|
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency
|
|
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys1.cache1.tags.replacements 63994 # number of replacements
|
|
system.l1subsys1.cache1.tags.tagsinuse 503.289590 # Cycle average of tags in use
|
|
system.l1subsys1.cache1.tags.total_refs 28611 # Total number of references to valid blocks.
|
|
system.l1subsys1.cache1.tags.sampled_refs 64495 # Sample count of references to valid blocks.
|
|
system.l1subsys1.cache1.tags.avg_refs 0.443616 # Average number of references to valid blocks.
|
|
system.l1subsys1.cache1.tags.warmup_cycle 273027000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester0 252.648267 # Average occupied blocks per requestor
|
|
system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester1 250.641323 # Average occupied blocks per requestor
|
|
system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester0 0.493454 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester1 0.489534 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache1.tags.occ_percent::total 0.982987 # Average percentage of cache occupancy
|
|
system.l1subsys1.cache1.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id
|
|
system.l1subsys1.cache1.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
|
system.l1subsys1.cache1.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
|
|
system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
|
|
system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
|
|
system.l1subsys1.cache1.tags.tag_accesses 622355 # Number of tag accesses
|
|
system.l1subsys1.cache1.tags.data_accesses 622355 # Number of data accesses
|
|
system.l1subsys1.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 8800 # number of ReadReq hits
|
|
system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9171 # number of ReadReq hits
|
|
system.l1subsys1.cache1.ReadReq_hits::total 17971 # number of ReadReq hits
|
|
system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester0 1063 # number of WriteReq hits
|
|
system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester1 1139 # number of WriteReq hits
|
|
system.l1subsys1.cache1.WriteReq_hits::total 2202 # number of WriteReq hits
|
|
system.l1subsys1.cache1.demand_hits::l0subsys3.tester0 9863 # number of demand (read+write) hits
|
|
system.l1subsys1.cache1.demand_hits::l0subsys3.tester1 10310 # number of demand (read+write) hits
|
|
system.l1subsys1.cache1.demand_hits::total 20173 # number of demand (read+write) hits
|
|
system.l1subsys1.cache1.overall_hits::l0subsys3.tester0 9863 # number of overall hits
|
|
system.l1subsys1.cache1.overall_hits::l0subsys3.tester1 10310 # number of overall hits
|
|
system.l1subsys1.cache1.overall_hits::total 20173 # number of overall hits
|
|
system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester0 33078 # number of ReadReq misses
|
|
system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester1 32783 # number of ReadReq misses
|
|
system.l1subsys1.cache1.ReadReq_misses::total 65861 # number of ReadReq misses
|
|
system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester0 22069 # number of WriteReq misses
|
|
system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester1 22457 # number of WriteReq misses
|
|
system.l1subsys1.cache1.WriteReq_misses::total 44526 # number of WriteReq misses
|
|
system.l1subsys1.cache1.demand_misses::l0subsys3.tester0 55147 # number of demand (read+write) misses
|
|
system.l1subsys1.cache1.demand_misses::l0subsys3.tester1 55240 # number of demand (read+write) misses
|
|
system.l1subsys1.cache1.demand_misses::total 110387 # number of demand (read+write) misses
|
|
system.l1subsys1.cache1.overall_misses::l0subsys3.tester0 55147 # number of overall misses
|
|
system.l1subsys1.cache1.overall_misses::l0subsys3.tester1 55240 # number of overall misses
|
|
system.l1subsys1.cache1.overall_misses::total 110387 # number of overall misses
|
|
system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester0 2996863885 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester1 2917691560 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache1.ReadReq_miss_latency::total 5914555445 # number of ReadReq miss cycles
|
|
system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester0 1848193916 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester1 1820903145 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache1.WriteReq_miss_latency::total 3669097061 # number of WriteReq miss cycles
|
|
system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester0 4845057801 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester1 4738594705 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache1.demand_miss_latency::total 9583652506 # number of demand (read+write) miss cycles
|
|
system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester0 4845057801 # number of overall miss cycles
|
|
system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester1 4738594705 # number of overall miss cycles
|
|
system.l1subsys1.cache1.overall_miss_latency::total 9583652506 # number of overall miss cycles
|
|
system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester0 41878 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester1 41954 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.ReadReq_accesses::total 83832 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester0 23132 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester1 23596 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.WriteReq_accesses::total 46728 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys1.cache1.demand_accesses::l0subsys3.tester0 65010 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache1.demand_accesses::l0subsys3.tester1 65550 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache1.demand_accesses::total 130560 # number of demand (read+write) accesses
|
|
system.l1subsys1.cache1.overall_accesses::l0subsys3.tester0 65010 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache1.overall_accesses::l0subsys3.tester1 65550 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache1.overall_accesses::total 130560 # number of overall (read+write) accesses
|
|
system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester0 0.789866 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester1 0.781403 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.ReadReq_miss_rate::total 0.785631 # miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester0 0.954046 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester1 0.951729 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.WriteReq_miss_rate::total 0.952876 # miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester0 0.848285 # miss rate for demand accesses
|
|
system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester1 0.842715 # miss rate for demand accesses
|
|
system.l1subsys1.cache1.demand_miss_rate::total 0.845489 # miss rate for demand accesses
|
|
system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester0 0.848285 # miss rate for overall accesses
|
|
system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester1 0.842715 # miss rate for overall accesses
|
|
system.l1subsys1.cache1.overall_miss_rate::total 0.845489 # miss rate for overall accesses
|
|
system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester0 90599.911875 # average ReadReq miss latency
|
|
system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester1 89000.139096 # average ReadReq miss latency
|
|
system.l1subsys1.cache1.ReadReq_avg_miss_latency::total 89803.608281 # average ReadReq miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester0 83746.155965 # average WriteReq miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester1 81083.989179 # average WriteReq miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_miss_latency::total 82403.473499 # average WriteReq miss latency
|
|
system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency
|
|
system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency
|
|
system.l1subsys1.cache1.demand_avg_miss_latency::total 86818.669825 # average overall miss latency
|
|
system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency
|
|
system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency
|
|
system.l1subsys1.cache1.overall_avg_miss_latency::total 86818.669825 # average overall miss latency
|
|
system.l1subsys1.cache1.blocked_cycles::no_mshrs 248811 # number of cycles access was blocked
|
|
system.l1subsys1.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys1.cache1.blocked::no_mshrs 7700 # number of cycles access was blocked
|
|
system.l1subsys1.cache1.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys1.cache1.avg_blocked_cycles::no_mshrs 32.313117 # average number of cycles each access was blocked
|
|
system.l1subsys1.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys1.cache1.writebacks::writebacks 23111 # number of writebacks
|
|
system.l1subsys1.cache1.writebacks::total 23111 # number of writebacks
|
|
system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester0 1265 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester1 1191 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache1.ReadReq_mshr_hits::total 2456 # number of ReadReq MSHR hits
|
|
system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester0 636 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester1 652 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache1.WriteReq_mshr_hits::total 1288 # number of WriteReq MSHR hits
|
|
system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester0 1901 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester1 1843 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache1.demand_mshr_hits::total 3744 # number of demand (read+write) MSHR hits
|
|
system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester0 1901 # number of overall MSHR hits
|
|
system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester1 1843 # number of overall MSHR hits
|
|
system.l1subsys1.cache1.overall_mshr_hits::total 3744 # number of overall MSHR hits
|
|
system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester0 31813 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester1 31592 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache1.ReadReq_mshr_misses::total 63405 # number of ReadReq MSHR misses
|
|
system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester0 21433 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester1 21805 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache1.WriteReq_mshr_misses::total 43238 # number of WriteReq MSHR misses
|
|
system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester0 53246 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester1 53397 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache1.demand_mshr_misses::total 106643 # number of demand (read+write) MSHR misses
|
|
system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester0 53246 # number of overall MSHR misses
|
|
system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester1 53397 # number of overall MSHR misses
|
|
system.l1subsys1.cache1.overall_mshr_misses::total 106643 # number of overall MSHR misses
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester0 2936678534 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester1 2859058481 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_latency::total 5795737015 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester0 1817912539 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester1 1790790455 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_latency::total 3608702994 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache1.demand_mshr_miss_latency::total 9404440009 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache1.overall_mshr_miss_latency::total 9404440009 # number of overall MSHR miss cycles
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester0 0.759659 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester1 0.753015 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.ReadReq_mshr_miss_rate::total 0.756334 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester0 0.926552 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester1 0.924097 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.WriteReq_mshr_miss_rate::total 0.925312 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache1.demand_mshr_miss_rate::total 0.816812 # mshr miss rate for demand accesses
|
|
system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache1.overall_mshr_miss_rate::total 0.816812 # mshr miss rate for overall accesses
|
|
system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester0 92310.644516 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester1 90499.445461 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::total 91408.201483 # average ReadReq mshr miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester0 84818.389353 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester1 82127.514561 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::total 83461.376428 # average WriteReq mshr miss latency
|
|
system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.demand_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency
|
|
system.l1subsys1.cache1.overall_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency
|
|
system.l1subsys1.xbar.snoop_filter.tot_requests 340971 # Total number of requests made to the snoop filter.
|
|
system.l1subsys1.xbar.snoop_filter.hit_single_requests 160937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys1.xbar.snoop_filter.hit_multi_requests 9094 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys1.xbar.snoop_filter.tot_snoops 156359 # Total number of snoops made to the snoop filter.
|
|
system.l1subsys1.xbar.snoop_filter.hit_single_snoops 137796 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 18563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys1.xbar.trans_dist::ReadResp 153671 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 4438 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::WritebackDirty 90488 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::CleanEvict 185296 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::UpgradeReq 38860 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::UpgradeResp 23637 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::ReadExReq 102525 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::ReadExResp 93076 # Transaction distribution
|
|
system.l1subsys1.xbar.trans_dist::ReadSharedReq 169429 # Transaction distribution
|
|
system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 299650 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 300840 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.pkt_count::total 600490 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 9042560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 9075776 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.pkt_size::total 18118336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys1.xbar.snoops 321671 # Total snoops (count)
|
|
system.l1subsys1.xbar.snoopTraffic 7090944 # Total snoop traffic (bytes)
|
|
system.l1subsys1.xbar.snoop_fanout::samples 459710 # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::mean 0.443486 # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::stdev 0.572334 # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::0 274398 59.69% 59.69% # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::1 166749 36.27% 95.96% # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::2 18563 4.04% 100.00% # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.l1subsys1.xbar.snoop_fanout::total 459710 # Request fanout histogram
|
|
system.l1subsys1.xbar.reqLayer0.occupancy 530478299 # Layer occupancy (ticks)
|
|
system.l1subsys1.xbar.reqLayer0.utilization 5.3 # Layer utilization (%)
|
|
system.l1subsys1.xbar.snoopLayer0.occupancy 184704449 # Layer occupancy (ticks)
|
|
system.l1subsys1.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
|
|
system.l1subsys1.xbar.respLayer0.occupancy 310357504 # Layer occupancy (ticks)
|
|
system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
|
|
system.l1subsys1.xbar.respLayer1.occupancy 313853796 # Layer occupancy (ticks)
|
|
system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%)
|
|
system.l1subsys2.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys2.cache0.tags.replacements 66509 # number of replacements
|
|
system.l1subsys2.cache0.tags.tagsinuse 503.868093 # Cycle average of tags in use
|
|
system.l1subsys2.cache0.tags.total_refs 30279 # Total number of references to valid blocks.
|
|
system.l1subsys2.cache0.tags.sampled_refs 67016 # Sample count of references to valid blocks.
|
|
system.l1subsys2.cache0.tags.avg_refs 0.451817 # Average number of references to valid blocks.
|
|
system.l1subsys2.cache0.tags.warmup_cycle 829394000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester0 256.450231 # Average occupied blocks per requestor
|
|
system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester1 247.417862 # Average occupied blocks per requestor
|
|
system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester0 0.500879 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester1 0.483238 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache0.tags.occ_percent::total 0.984117 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id
|
|
system.l1subsys2.cache0.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
|
|
system.l1subsys2.cache0.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id
|
|
system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
|
system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id
|
|
system.l1subsys2.cache0.tags.tag_accesses 631189 # Number of tag accesses
|
|
system.l1subsys2.cache0.tags.data_accesses 631189 # Number of data accesses
|
|
system.l1subsys2.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10236 # number of ReadReq hits
|
|
system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 8788 # number of ReadReq hits
|
|
system.l1subsys2.cache0.ReadReq_hits::total 19024 # number of ReadReq hits
|
|
system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester0 1819 # number of WriteReq hits
|
|
system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester1 1004 # number of WriteReq hits
|
|
system.l1subsys2.cache0.WriteReq_hits::total 2823 # number of WriteReq hits
|
|
system.l1subsys2.cache0.demand_hits::l0subsys4.tester0 12055 # number of demand (read+write) hits
|
|
system.l1subsys2.cache0.demand_hits::l0subsys4.tester1 9792 # number of demand (read+write) hits
|
|
system.l1subsys2.cache0.demand_hits::total 21847 # number of demand (read+write) hits
|
|
system.l1subsys2.cache0.overall_hits::l0subsys4.tester0 12055 # number of overall hits
|
|
system.l1subsys2.cache0.overall_hits::l0subsys4.tester1 9792 # number of overall hits
|
|
system.l1subsys2.cache0.overall_hits::total 21847 # number of overall hits
|
|
system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester0 32304 # number of ReadReq misses
|
|
system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester1 34007 # number of ReadReq misses
|
|
system.l1subsys2.cache0.ReadReq_misses::total 66311 # number of ReadReq misses
|
|
system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester0 21653 # number of WriteReq misses
|
|
system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester1 22755 # number of WriteReq misses
|
|
system.l1subsys2.cache0.WriteReq_misses::total 44408 # number of WriteReq misses
|
|
system.l1subsys2.cache0.demand_misses::l0subsys4.tester0 53957 # number of demand (read+write) misses
|
|
system.l1subsys2.cache0.demand_misses::l0subsys4.tester1 56762 # number of demand (read+write) misses
|
|
system.l1subsys2.cache0.demand_misses::total 110719 # number of demand (read+write) misses
|
|
system.l1subsys2.cache0.overall_misses::l0subsys4.tester0 53957 # number of overall misses
|
|
system.l1subsys2.cache0.overall_misses::l0subsys4.tester1 56762 # number of overall misses
|
|
system.l1subsys2.cache0.overall_misses::total 110719 # number of overall misses
|
|
system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester0 3033418520 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester1 3062242477 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache0.ReadReq_miss_latency::total 6095660997 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester0 1821498988 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester1 1866435160 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache0.WriteReq_miss_latency::total 3687934148 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester0 4854917508 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester1 4928677637 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache0.demand_miss_latency::total 9783595145 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester0 4854917508 # number of overall miss cycles
|
|
system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester1 4928677637 # number of overall miss cycles
|
|
system.l1subsys2.cache0.overall_miss_latency::total 9783595145 # number of overall miss cycles
|
|
system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester0 42540 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester1 42795 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.ReadReq_accesses::total 85335 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester0 23472 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester1 23759 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.WriteReq_accesses::total 47231 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache0.demand_accesses::l0subsys4.tester0 66012 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache0.demand_accesses::l0subsys4.tester1 66554 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache0.demand_accesses::total 132566 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache0.overall_accesses::l0subsys4.tester0 66012 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache0.overall_accesses::l0subsys4.tester1 66554 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache0.overall_accesses::total 132566 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester0 0.759379 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester1 0.794649 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.ReadReq_miss_rate::total 0.777067 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester0 0.922503 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester1 0.957742 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.WriteReq_miss_rate::total 0.940230 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester0 0.817382 # miss rate for demand accesses
|
|
system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester1 0.852871 # miss rate for demand accesses
|
|
system.l1subsys2.cache0.demand_miss_rate::total 0.835199 # miss rate for demand accesses
|
|
system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester0 0.817382 # miss rate for overall accesses
|
|
system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester1 0.852871 # miss rate for overall accesses
|
|
system.l1subsys2.cache0.overall_miss_rate::total 0.835199 # miss rate for overall accesses
|
|
system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester0 93902.257306 # average ReadReq miss latency
|
|
system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester1 90047.416032 # average ReadReq miss latency
|
|
system.l1subsys2.cache0.ReadReq_avg_miss_latency::total 91925.336626 # average ReadReq miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester0 84122.245786 # average WriteReq miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester1 82023.078884 # average WriteReq miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_miss_latency::total 83046.616556 # average WriteReq miss latency
|
|
system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency
|
|
system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency
|
|
system.l1subsys2.cache0.demand_avg_miss_latency::total 88364.193544 # average overall miss latency
|
|
system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency
|
|
system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency
|
|
system.l1subsys2.cache0.overall_avg_miss_latency::total 88364.193544 # average overall miss latency
|
|
system.l1subsys2.cache0.blocked_cycles::no_mshrs 263390 # number of cycles access was blocked
|
|
system.l1subsys2.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys2.cache0.blocked::no_mshrs 8190 # number of cycles access was blocked
|
|
system.l1subsys2.cache0.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys2.cache0.avg_blocked_cycles::no_mshrs 32.159951 # average number of cycles each access was blocked
|
|
system.l1subsys2.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys2.cache0.writebacks::writebacks 23607 # number of writebacks
|
|
system.l1subsys2.cache0.writebacks::total 23607 # number of writebacks
|
|
system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester0 970 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester1 984 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache0.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester0 557 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester1 530 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache0.WriteReq_mshr_hits::total 1087 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester0 1527 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester1 1514 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache0.demand_mshr_hits::total 3041 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester0 1527 # number of overall MSHR hits
|
|
system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester1 1514 # number of overall MSHR hits
|
|
system.l1subsys2.cache0.overall_mshr_hits::total 3041 # number of overall MSHR hits
|
|
system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester0 31334 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester1 33023 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache0.ReadReq_mshr_misses::total 64357 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester0 21096 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester1 22225 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache0.WriteReq_mshr_misses::total 43321 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester0 52430 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester1 55248 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache0.demand_mshr_misses::total 107678 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester0 52430 # number of overall MSHR misses
|
|
system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester1 55248 # number of overall MSHR misses
|
|
system.l1subsys2.cache0.overall_mshr_misses::total 107678 # number of overall MSHR misses
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester0 2981407825 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester1 3008088243 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_latency::total 5989496068 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester0 1792490103 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester1 1837443596 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_latency::total 3629933699 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache0.demand_mshr_miss_latency::total 9619429767 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache0.overall_mshr_miss_latency::total 9619429767 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester0 0.736577 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester1 0.771656 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.ReadReq_mshr_miss_rate::total 0.754169 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester0 0.898773 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester1 0.935435 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.WriteReq_mshr_miss_rate::total 0.917215 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache0.demand_mshr_miss_rate::total 0.812260 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache0.overall_mshr_miss_rate::total 0.812260 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester0 95149.289111 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester1 91090.701723 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::total 93066.738164 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester0 84968.245307 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester1 82674.627492 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::total 83791.549110 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency
|
|
system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency
|
|
system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency
|
|
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency
|
|
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency
|
|
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys2.cache1.tags.replacements 65601 # number of replacements
|
|
system.l1subsys2.cache1.tags.tagsinuse 502.970157 # Cycle average of tags in use
|
|
system.l1subsys2.cache1.tags.total_refs 28017 # Total number of references to valid blocks.
|
|
system.l1subsys2.cache1.tags.sampled_refs 66106 # Sample count of references to valid blocks.
|
|
system.l1subsys2.cache1.tags.avg_refs 0.423819 # Average number of references to valid blocks.
|
|
system.l1subsys2.cache1.tags.warmup_cycle 368043000 # Cycle when the warmup percentage was hit.
|
|
system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester0 256.035642 # Average occupied blocks per requestor
|
|
system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester1 246.934515 # Average occupied blocks per requestor
|
|
system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester0 0.500070 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester1 0.482294 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache1.tags.occ_percent::total 0.982364 # Average percentage of cache occupancy
|
|
system.l1subsys2.cache1.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id
|
|
system.l1subsys2.cache1.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
|
system.l1subsys2.cache1.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
|
|
system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
|
|
system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id
|
|
system.l1subsys2.cache1.tags.tag_accesses 631185 # Number of tag accesses
|
|
system.l1subsys2.cache1.tags.data_accesses 631185 # Number of data accesses
|
|
system.l1subsys2.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 8598 # number of ReadReq hits
|
|
system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 8958 # number of ReadReq hits
|
|
system.l1subsys2.cache1.ReadReq_hits::total 17556 # number of ReadReq hits
|
|
system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester0 971 # number of WriteReq hits
|
|
system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester1 994 # number of WriteReq hits
|
|
system.l1subsys2.cache1.WriteReq_hits::total 1965 # number of WriteReq hits
|
|
system.l1subsys2.cache1.demand_hits::l0subsys5.tester0 9569 # number of demand (read+write) hits
|
|
system.l1subsys2.cache1.demand_hits::l0subsys5.tester1 9952 # number of demand (read+write) hits
|
|
system.l1subsys2.cache1.demand_hits::total 19521 # number of demand (read+write) hits
|
|
system.l1subsys2.cache1.overall_hits::l0subsys5.tester0 9569 # number of overall hits
|
|
system.l1subsys2.cache1.overall_hits::l0subsys5.tester1 9952 # number of overall hits
|
|
system.l1subsys2.cache1.overall_hits::total 19521 # number of overall hits
|
|
system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester0 34186 # number of ReadReq misses
|
|
system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester1 33576 # number of ReadReq misses
|
|
system.l1subsys2.cache1.ReadReq_misses::total 67762 # number of ReadReq misses
|
|
system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester0 22463 # number of WriteReq misses
|
|
system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester1 22525 # number of WriteReq misses
|
|
system.l1subsys2.cache1.WriteReq_misses::total 44988 # number of WriteReq misses
|
|
system.l1subsys2.cache1.demand_misses::l0subsys5.tester0 56649 # number of demand (read+write) misses
|
|
system.l1subsys2.cache1.demand_misses::l0subsys5.tester1 56101 # number of demand (read+write) misses
|
|
system.l1subsys2.cache1.demand_misses::total 112750 # number of demand (read+write) misses
|
|
system.l1subsys2.cache1.overall_misses::l0subsys5.tester0 56649 # number of overall misses
|
|
system.l1subsys2.cache1.overall_misses::l0subsys5.tester1 56101 # number of overall misses
|
|
system.l1subsys2.cache1.overall_misses::total 112750 # number of overall misses
|
|
system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester0 3101171642 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester1 3046677897 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache1.ReadReq_miss_latency::total 6147849539 # number of ReadReq miss cycles
|
|
system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester0 1867972083 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester1 1852914357 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache1.WriteReq_miss_latency::total 3720886440 # number of WriteReq miss cycles
|
|
system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester0 4969143725 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester1 4899592254 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache1.demand_miss_latency::total 9868735979 # number of demand (read+write) miss cycles
|
|
system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester0 4969143725 # number of overall miss cycles
|
|
system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester1 4899592254 # number of overall miss cycles
|
|
system.l1subsys2.cache1.overall_miss_latency::total 9868735979 # number of overall miss cycles
|
|
system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester0 42784 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester1 42534 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester0 23434 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester1 23519 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.WriteReq_accesses::total 46953 # number of WriteReq accesses(hits+misses)
|
|
system.l1subsys2.cache1.demand_accesses::l0subsys5.tester0 66218 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache1.demand_accesses::l0subsys5.tester1 66053 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache1.demand_accesses::total 132271 # number of demand (read+write) accesses
|
|
system.l1subsys2.cache1.overall_accesses::l0subsys5.tester0 66218 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache1.overall_accesses::l0subsys5.tester1 66053 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache1.overall_accesses::total 132271 # number of overall (read+write) accesses
|
|
system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester0 0.799037 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester1 0.789392 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.ReadReq_miss_rate::total 0.794229 # miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester0 0.958564 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester1 0.957736 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.WriteReq_miss_rate::total 0.958150 # miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester0 0.855492 # miss rate for demand accesses
|
|
system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester1 0.849333 # miss rate for demand accesses
|
|
system.l1subsys2.cache1.demand_miss_rate::total 0.852417 # miss rate for demand accesses
|
|
system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester0 0.855492 # miss rate for overall accesses
|
|
system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester1 0.849333 # miss rate for overall accesses
|
|
system.l1subsys2.cache1.overall_miss_rate::total 0.852417 # miss rate for overall accesses
|
|
system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester0 90714.668051 # average ReadReq miss latency
|
|
system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester1 90739.751519 # average ReadReq miss latency
|
|
system.l1subsys2.cache1.ReadReq_avg_miss_latency::total 90727.096883 # average ReadReq miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester0 83157.729733 # average WriteReq miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester1 82260.348812 # average WriteReq miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_miss_latency::total 82708.420912 # average WriteReq miss latency
|
|
system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency
|
|
system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency
|
|
system.l1subsys2.cache1.demand_avg_miss_latency::total 87527.591831 # average overall miss latency
|
|
system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency
|
|
system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency
|
|
system.l1subsys2.cache1.overall_avg_miss_latency::total 87527.591831 # average overall miss latency
|
|
system.l1subsys2.cache1.blocked_cycles::no_mshrs 243675 # number of cycles access was blocked
|
|
system.l1subsys2.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys2.cache1.blocked::no_mshrs 7511 # number of cycles access was blocked
|
|
system.l1subsys2.cache1.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l1subsys2.cache1.avg_blocked_cycles::no_mshrs 32.442418 # average number of cycles each access was blocked
|
|
system.l1subsys2.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l1subsys2.cache1.writebacks::writebacks 23261 # number of writebacks
|
|
system.l1subsys2.cache1.writebacks::total 23261 # number of writebacks
|
|
system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester0 1398 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester1 1315 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache1.ReadReq_mshr_hits::total 2713 # number of ReadReq MSHR hits
|
|
system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester0 724 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester1 737 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache1.WriteReq_mshr_hits::total 1461 # number of WriteReq MSHR hits
|
|
system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester0 2122 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester1 2052 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache1.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits
|
|
system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester0 2122 # number of overall MSHR hits
|
|
system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester1 2052 # number of overall MSHR hits
|
|
system.l1subsys2.cache1.overall_mshr_hits::total 4174 # number of overall MSHR hits
|
|
system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester0 32788 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester1 32261 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache1.ReadReq_mshr_misses::total 65049 # number of ReadReq MSHR misses
|
|
system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester0 21739 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester1 21788 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache1.WriteReq_mshr_misses::total 43527 # number of WriteReq MSHR misses
|
|
system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester0 54527 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester1 54049 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache1.demand_mshr_misses::total 108576 # number of demand (read+write) MSHR misses
|
|
system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester0 54527 # number of overall MSHR misses
|
|
system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester1 54049 # number of overall MSHR misses
|
|
system.l1subsys2.cache1.overall_mshr_misses::total 108576 # number of overall MSHR misses
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester0 3037090619 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester1 2984778636 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_latency::total 6021869255 # number of ReadReq MSHR miss cycles
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester0 1837384657 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester1 1821394302 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_latency::total 3658778959 # number of WriteReq MSHR miss cycles
|
|
system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache1.demand_mshr_miss_latency::total 9680648214 # number of demand (read+write) MSHR miss cycles
|
|
system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache1.overall_mshr_miss_latency::total 9680648214 # number of overall MSHR miss cycles
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester0 0.766361 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester1 0.758476 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.ReadReq_mshr_miss_rate::total 0.762430 # mshr miss rate for ReadReq accesses
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester0 0.927669 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester1 0.926400 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.WriteReq_mshr_miss_rate::total 0.927033 # mshr miss rate for WriteReq accesses
|
|
system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache1.demand_mshr_miss_rate::total 0.820860 # mshr miss rate for demand accesses
|
|
system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache1.overall_mshr_miss_rate::total 0.820860 # mshr miss rate for overall accesses
|
|
system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester0 92628.114524 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester1 92519.718422 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::total 92574.355563 # average ReadReq mshr miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester0 84520.201343 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester1 83596.213604 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::total 84057.687389 # average WriteReq mshr miss latency
|
|
system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.demand_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency
|
|
system.l1subsys2.cache1.overall_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency
|
|
system.l1subsys2.xbar.snoop_filter.tot_requests 350018 # Total number of requests made to the snoop filter.
|
|
system.l1subsys2.xbar.snoop_filter.hit_single_requests 165507 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8863 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys2.xbar.snoop_filter.tot_snoops 157282 # Total number of snoops made to the snoop filter.
|
|
system.l1subsys2.xbar.snoop_filter.hit_single_snoops 139819 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 17463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l1subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l1subsys2.xbar.trans_dist::ReadResp 155964 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 4483 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::WritebackDirty 93011 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::CleanEvict 193898 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::UpgradeReq 38837 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::UpgradeResp 23341 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::ReadExReq 102617 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::ReadExResp 93375 # Transaction distribution
|
|
system.l1subsys2.xbar.trans_dist::ReadSharedReq 171504 # Transaction distribution
|
|
system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 304422 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 307736 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.pkt_count::total 612158 # Packet count per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 9114816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 9277120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.pkt_size::total 18391936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l1subsys2.xbar.snoops 324128 # Total snoops (count)
|
|
system.l1subsys2.xbar.snoopTraffic 7056320 # Total snoop traffic (bytes)
|
|
system.l1subsys2.xbar.snoop_fanout::samples 467757 # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::mean 0.433484 # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::stdev 0.565900 # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::0 282455 60.38% 60.38% # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::1 167839 35.88% 96.27% # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::2 17463 3.73% 100.00% # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.l1subsys2.xbar.snoop_fanout::total 467757 # Request fanout histogram
|
|
system.l1subsys2.xbar.reqLayer0.occupancy 543938741 # Layer occupancy (ticks)
|
|
system.l1subsys2.xbar.reqLayer0.utilization 5.4 # Layer utilization (%)
|
|
system.l1subsys2.xbar.snoopLayer0.occupancy 179965490 # Layer occupancy (ticks)
|
|
system.l1subsys2.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%)
|
|
system.l1subsys2.xbar.respLayer0.occupancy 316289424 # Layer occupancy (ticks)
|
|
system.l1subsys2.xbar.respLayer0.utilization 3.2 # Layer utilization (%)
|
|
system.l1subsys2.xbar.respLayer1.occupancy 319642014 # Layer occupancy (ticks)
|
|
system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%)
|
|
system.l2subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache0.tags.replacements 33659 # number of replacements
|
|
system.l2subsys0.cache0.tags.tagsinuse 498.694876 # Cycle average of tags in use
|
|
system.l2subsys0.cache0.tags.total_refs 11307 # Total number of references to valid blocks.
|
|
system.l2subsys0.cache0.tags.sampled_refs 34163 # Sample count of references to valid blocks.
|
|
system.l2subsys0.cache0.tags.avg_refs 0.330972 # Average number of references to valid blocks.
|
|
system.l2subsys0.cache0.tags.warmup_cycle 1001764000 # Cycle when the warmup percentage was hit.
|
|
system.l2subsys0.cache0.tags.occ_blocks::l2subsys0.tester 498.694876 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache0.tags.occ_percent::l2subsys0.tester 0.974013 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache0.tags.occ_percent::total 0.974013 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
|
|
system.l2subsys0.cache0.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
|
|
system.l2subsys0.cache0.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
|
|
system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
|
|
system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
|
|
system.l2subsys0.cache0.tags.tag_accesses 325927 # Number of tag accesses
|
|
system.l2subsys0.cache0.tags.data_accesses 325927 # Number of data accesses
|
|
system.l2subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 7262 # number of ReadReq hits
|
|
system.l2subsys0.cache0.ReadReq_hits::total 7262 # number of ReadReq hits
|
|
system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 605 # number of WriteReq hits
|
|
system.l2subsys0.cache0.WriteReq_hits::total 605 # number of WriteReq hits
|
|
system.l2subsys0.cache0.demand_hits::l2subsys0.tester 7867 # number of demand (read+write) hits
|
|
system.l2subsys0.cache0.demand_hits::total 7867 # number of demand (read+write) hits
|
|
system.l2subsys0.cache0.overall_hits::l2subsys0.tester 7867 # number of overall hits
|
|
system.l2subsys0.cache0.overall_hits::total 7867 # number of overall hits
|
|
system.l2subsys0.cache0.ReadReq_misses::l2subsys0.tester 36028 # number of ReadReq misses
|
|
system.l2subsys0.cache0.ReadReq_misses::total 36028 # number of ReadReq misses
|
|
system.l2subsys0.cache0.WriteReq_misses::l2subsys0.tester 23553 # number of WriteReq misses
|
|
system.l2subsys0.cache0.WriteReq_misses::total 23553 # number of WriteReq misses
|
|
system.l2subsys0.cache0.demand_misses::l2subsys0.tester 59581 # number of demand (read+write) misses
|
|
system.l2subsys0.cache0.demand_misses::total 59581 # number of demand (read+write) misses
|
|
system.l2subsys0.cache0.overall_misses::l2subsys0.tester 59581 # number of overall misses
|
|
system.l2subsys0.cache0.overall_misses::total 59581 # number of overall misses
|
|
system.l2subsys0.cache0.ReadReq_miss_latency::l2subsys0.tester 2432084535 # number of ReadReq miss cycles
|
|
system.l2subsys0.cache0.ReadReq_miss_latency::total 2432084535 # number of ReadReq miss cycles
|
|
system.l2subsys0.cache0.WriteReq_miss_latency::l2subsys0.tester 1416934536 # number of WriteReq miss cycles
|
|
system.l2subsys0.cache0.WriteReq_miss_latency::total 1416934536 # number of WriteReq miss cycles
|
|
system.l2subsys0.cache0.demand_miss_latency::l2subsys0.tester 3849019071 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache0.demand_miss_latency::total 3849019071 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache0.overall_miss_latency::l2subsys0.tester 3849019071 # number of overall miss cycles
|
|
system.l2subsys0.cache0.overall_miss_latency::total 3849019071 # number of overall miss cycles
|
|
system.l2subsys0.cache0.ReadReq_accesses::l2subsys0.tester 43290 # number of ReadReq accesses(hits+misses)
|
|
system.l2subsys0.cache0.ReadReq_accesses::total 43290 # number of ReadReq accesses(hits+misses)
|
|
system.l2subsys0.cache0.WriteReq_accesses::l2subsys0.tester 24158 # number of WriteReq accesses(hits+misses)
|
|
system.l2subsys0.cache0.WriteReq_accesses::total 24158 # number of WriteReq accesses(hits+misses)
|
|
system.l2subsys0.cache0.demand_accesses::l2subsys0.tester 67448 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache0.demand_accesses::total 67448 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache0.overall_accesses::l2subsys0.tester 67448 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache0.overall_accesses::total 67448 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache0.ReadReq_miss_rate::l2subsys0.tester 0.832248 # miss rate for ReadReq accesses
|
|
system.l2subsys0.cache0.ReadReq_miss_rate::total 0.832248 # miss rate for ReadReq accesses
|
|
system.l2subsys0.cache0.WriteReq_miss_rate::l2subsys0.tester 0.974957 # miss rate for WriteReq accesses
|
|
system.l2subsys0.cache0.WriteReq_miss_rate::total 0.974957 # miss rate for WriteReq accesses
|
|
system.l2subsys0.cache0.demand_miss_rate::l2subsys0.tester 0.883362 # miss rate for demand accesses
|
|
system.l2subsys0.cache0.demand_miss_rate::total 0.883362 # miss rate for demand accesses
|
|
system.l2subsys0.cache0.overall_miss_rate::l2subsys0.tester 0.883362 # miss rate for overall accesses
|
|
system.l2subsys0.cache0.overall_miss_rate::total 0.883362 # miss rate for overall accesses
|
|
system.l2subsys0.cache0.ReadReq_avg_miss_latency::l2subsys0.tester 67505.399550 # average ReadReq miss latency
|
|
system.l2subsys0.cache0.ReadReq_avg_miss_latency::total 67505.399550 # average ReadReq miss latency
|
|
system.l2subsys0.cache0.WriteReq_avg_miss_latency::l2subsys0.tester 60159.407974 # average WriteReq miss latency
|
|
system.l2subsys0.cache0.WriteReq_avg_miss_latency::total 60159.407974 # average WriteReq miss latency
|
|
system.l2subsys0.cache0.demand_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency
|
|
system.l2subsys0.cache0.demand_avg_miss_latency::total 64601.451318 # average overall miss latency
|
|
system.l2subsys0.cache0.overall_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency
|
|
system.l2subsys0.cache0.overall_avg_miss_latency::total 64601.451318 # average overall miss latency
|
|
system.l2subsys0.cache0.blocked_cycles::no_mshrs 22051 # number of cycles access was blocked
|
|
system.l2subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache0.blocked::no_mshrs 434 # number of cycles access was blocked
|
|
system.l2subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache0.avg_blocked_cycles::no_mshrs 50.808756 # average number of cycles each access was blocked
|
|
system.l2subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache0.writebacks::writebacks 12098 # number of writebacks
|
|
system.l2subsys0.cache0.writebacks::total 12098 # number of writebacks
|
|
system.l2subsys0.cache0.ReadReq_mshr_hits::l2subsys0.tester 8 # number of ReadReq MSHR hits
|
|
system.l2subsys0.cache0.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
system.l2subsys0.cache0.WriteReq_mshr_hits::l2subsys0.tester 6 # number of WriteReq MSHR hits
|
|
system.l2subsys0.cache0.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits
|
|
system.l2subsys0.cache0.demand_mshr_hits::l2subsys0.tester 14 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache0.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache0.overall_mshr_hits::l2subsys0.tester 14 # number of overall MSHR hits
|
|
system.l2subsys0.cache0.overall_mshr_hits::total 14 # number of overall MSHR hits
|
|
system.l2subsys0.cache0.ReadReq_mshr_misses::l2subsys0.tester 36020 # number of ReadReq MSHR misses
|
|
system.l2subsys0.cache0.ReadReq_mshr_misses::total 36020 # number of ReadReq MSHR misses
|
|
system.l2subsys0.cache0.WriteReq_mshr_misses::l2subsys0.tester 23547 # number of WriteReq MSHR misses
|
|
system.l2subsys0.cache0.WriteReq_mshr_misses::total 23547 # number of WriteReq MSHR misses
|
|
system.l2subsys0.cache0.demand_mshr_misses::l2subsys0.tester 59567 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache0.demand_mshr_misses::total 59567 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache0.overall_mshr_misses::l2subsys0.tester 59567 # number of overall MSHR misses
|
|
system.l2subsys0.cache0.overall_mshr_misses::total 59567 # number of overall MSHR misses
|
|
system.l2subsys0.cache0.ReadReq_mshr_miss_latency::l2subsys0.tester 2396005584 # number of ReadReq MSHR miss cycles
|
|
system.l2subsys0.cache0.ReadReq_mshr_miss_latency::total 2396005584 # number of ReadReq MSHR miss cycles
|
|
system.l2subsys0.cache0.WriteReq_mshr_miss_latency::l2subsys0.tester 1393365242 # number of WriteReq MSHR miss cycles
|
|
system.l2subsys0.cache0.WriteReq_mshr_miss_latency::total 1393365242 # number of WriteReq MSHR miss cycles
|
|
system.l2subsys0.cache0.demand_mshr_miss_latency::l2subsys0.tester 3789370826 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache0.demand_mshr_miss_latency::total 3789370826 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache0.overall_mshr_miss_latency::l2subsys0.tester 3789370826 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache0.overall_mshr_miss_latency::total 3789370826 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache0.ReadReq_mshr_miss_rate::l2subsys0.tester 0.832063 # mshr miss rate for ReadReq accesses
|
|
system.l2subsys0.cache0.ReadReq_mshr_miss_rate::total 0.832063 # mshr miss rate for ReadReq accesses
|
|
system.l2subsys0.cache0.WriteReq_mshr_miss_rate::l2subsys0.tester 0.974708 # mshr miss rate for WriteReq accesses
|
|
system.l2subsys0.cache0.WriteReq_mshr_miss_rate::total 0.974708 # mshr miss rate for WriteReq accesses
|
|
system.l2subsys0.cache0.demand_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache0.demand_mshr_miss_rate::total 0.883154 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache0.overall_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache0.overall_mshr_miss_rate::total 0.883154 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::l2subsys0.tester 66518.755802 # average ReadReq mshr miss latency
|
|
system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 66518.755802 # average ReadReq mshr miss latency
|
|
system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::l2subsys0.tester 59173.790377 # average WriteReq mshr miss latency
|
|
system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 59173.790377 # average WriteReq mshr miss latency
|
|
system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency
|
|
system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency
|
|
system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency
|
|
system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache1.tags.replacements 151853 # number of replacements
|
|
system.l2subsys0.cache1.tags.tagsinuse 1524.082956 # Cycle average of tags in use
|
|
system.l2subsys0.cache1.tags.total_refs 82258 # Total number of references to valid blocks.
|
|
system.l2subsys0.cache1.tags.sampled_refs 153387 # Sample count of references to valid blocks.
|
|
system.l2subsys0.cache1.tags.avg_refs 0.536278 # Average number of references to valid blocks.
|
|
system.l2subsys0.cache1.tags.warmup_cycle 439051000 # Cycle when the warmup percentage was hit.
|
|
system.l2subsys0.cache1.tags.occ_blocks::writebacks 190.667622 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester0 328.055957 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester1 322.496146 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 335.799241 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 347.063989 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache1.tags.occ_percent::writebacks 0.124133 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester0 0.213578 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester1 0.209958 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.218619 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.225953 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_percent::total 0.992242 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache1.tags.occ_task_id_blocks::1024 1534 # Occupied blocks per task id
|
|
system.l2subsys0.cache1.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
|
system.l2subsys0.cache1.tags.age_task_id_blocks_1024::1 1102 # Occupied blocks per task id
|
|
system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
|
|
system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.998698 # Percentage of cache occupancy per task id
|
|
system.l2subsys0.cache1.tags.tag_accesses 4165543 # Number of tag accesses
|
|
system.l2subsys0.cache1.tags.data_accesses 4165543 # Number of data accesses
|
|
system.l2subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache1.WritebackDirty_hits::writebacks 46587 # number of WritebackDirty hits
|
|
system.l2subsys0.cache1.WritebackDirty_hits::total 46587 # number of WritebackDirty hits
|
|
system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester0 168 # number of UpgradeReq hits
|
|
system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester1 121 # number of UpgradeReq hits
|
|
system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester0 142 # number of UpgradeReq hits
|
|
system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester1 160 # number of UpgradeReq hits
|
|
system.l2subsys0.cache1.UpgradeReq_hits::total 591 # number of UpgradeReq hits
|
|
system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 42 # number of ReadExReq hits
|
|
system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester1 49 # number of ReadExReq hits
|
|
system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester0 38 # number of ReadExReq hits
|
|
system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester1 33 # number of ReadExReq hits
|
|
system.l2subsys0.cache1.ReadExReq_hits::total 162 # number of ReadExReq hits
|
|
system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester0 686 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester1 632 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester0 726 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester1 731 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache1.ReadSharedReq_hits::total 2775 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache1.demand_hits::l0subsys0.tester0 728 # number of demand (read+write) hits
|
|
system.l2subsys0.cache1.demand_hits::l0subsys0.tester1 681 # number of demand (read+write) hits
|
|
system.l2subsys0.cache1.demand_hits::l0subsys1.tester0 764 # number of demand (read+write) hits
|
|
system.l2subsys0.cache1.demand_hits::l0subsys1.tester1 764 # number of demand (read+write) hits
|
|
system.l2subsys0.cache1.demand_hits::total 2937 # number of demand (read+write) hits
|
|
system.l2subsys0.cache1.overall_hits::l0subsys0.tester0 728 # number of overall hits
|
|
system.l2subsys0.cache1.overall_hits::l0subsys0.tester1 681 # number of overall hits
|
|
system.l2subsys0.cache1.overall_hits::l0subsys1.tester0 764 # number of overall hits
|
|
system.l2subsys0.cache1.overall_hits::l0subsys1.tester1 764 # number of overall hits
|
|
system.l2subsys0.cache1.overall_hits::total 2937 # number of overall hits
|
|
system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester0 3496 # number of UpgradeReq misses
|
|
system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester1 3545 # number of UpgradeReq misses
|
|
system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester0 3229 # number of UpgradeReq misses
|
|
system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester1 3694 # number of UpgradeReq misses
|
|
system.l2subsys0.cache1.UpgradeReq_misses::total 13964 # number of UpgradeReq misses
|
|
system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester0 16533 # number of ReadExReq misses
|
|
system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester1 16684 # number of ReadExReq misses
|
|
system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester0 16775 # number of ReadExReq misses
|
|
system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester1 16964 # number of ReadExReq misses
|
|
system.l2subsys0.cache1.ReadExReq_misses::total 66956 # number of ReadExReq misses
|
|
system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester0 28808 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester1 29088 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester0 28899 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester1 29649 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache1.ReadSharedReq_misses::total 116444 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache1.demand_misses::l0subsys0.tester0 45341 # number of demand (read+write) misses
|
|
system.l2subsys0.cache1.demand_misses::l0subsys0.tester1 45772 # number of demand (read+write) misses
|
|
system.l2subsys0.cache1.demand_misses::l0subsys1.tester0 45674 # number of demand (read+write) misses
|
|
system.l2subsys0.cache1.demand_misses::l0subsys1.tester1 46613 # number of demand (read+write) misses
|
|
system.l2subsys0.cache1.demand_misses::total 183400 # number of demand (read+write) misses
|
|
system.l2subsys0.cache1.overall_misses::l0subsys0.tester0 45341 # number of overall misses
|
|
system.l2subsys0.cache1.overall_misses::l0subsys0.tester1 45772 # number of overall misses
|
|
system.l2subsys0.cache1.overall_misses::l0subsys1.tester0 45674 # number of overall misses
|
|
system.l2subsys0.cache1.overall_misses::l0subsys1.tester1 46613 # number of overall misses
|
|
system.l2subsys0.cache1.overall_misses::total 183400 # number of overall misses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester0 113867429 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester1 115764935 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester0 105593459 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester1 122664883 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_miss_latency::total 457890706 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester0 1586451745 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester1 1553900027 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester0 1610224177 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester1 1616496304 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_miss_latency::total 6367072253 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester0 2779939089 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester1 2733735321 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester0 2766545210 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester1 2839007144 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_latency::total 11119226764 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester0 4366390834 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester1 4287635348 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4376769387 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4455503448 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache1.demand_miss_latency::total 17486299017 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester0 4366390834 # number of overall miss cycles
|
|
system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester1 4287635348 # number of overall miss cycles
|
|
system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4376769387 # number of overall miss cycles
|
|
system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4455503448 # number of overall miss cycles
|
|
system.l2subsys0.cache1.overall_miss_latency::total 17486299017 # number of overall miss cycles
|
|
system.l2subsys0.cache1.WritebackDirty_accesses::writebacks 46587 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache1.WritebackDirty_accesses::total 46587 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester0 3664 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester1 3666 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester0 3371 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester1 3854 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.UpgradeReq_accesses::total 14555 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester0 16575 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester1 16733 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester0 16813 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester1 16997 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadExReq_accesses::total 67118 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester0 29494 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester1 29720 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester0 29625 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester1 30380 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.ReadSharedReq_accesses::total 119219 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache1.demand_accesses::l0subsys0.tester0 46069 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache1.demand_accesses::l0subsys0.tester1 46453 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache1.demand_accesses::l0subsys1.tester0 46438 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache1.demand_accesses::l0subsys1.tester1 47377 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache1.demand_accesses::total 186337 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache1.overall_accesses::l0subsys0.tester0 46069 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache1.overall_accesses::l0subsys0.tester1 46453 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache1.overall_accesses::l0subsys1.tester0 46438 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache1.overall_accesses::l0subsys1.tester1 47377 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache1.overall_accesses::total 186337 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester0 0.954148 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester1 0.966994 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester0 0.957876 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester1 0.958485 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_miss_rate::total 0.959395 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester0 0.997466 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester1 0.997072 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester0 0.997740 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester1 0.998058 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_miss_rate::total 0.997586 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester0 0.976741 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester1 0.978735 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester0 0.975494 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester1 0.975938 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_miss_rate::total 0.976724 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester0 0.984198 # miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester1 0.985340 # miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.983548 # miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.983874 # miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_miss_rate::total 0.984238 # miss rate for demand accesses
|
|
system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester0 0.984198 # miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester1 0.985340 # miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.983548 # miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.983874 # miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_miss_rate::total 0.984238 # miss rate for overall accesses
|
|
system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester0 32570.774886 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester1 32655.834979 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester0 32701.597708 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester1 33206.519491 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::total 32790.798195 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester0 95956.677252 # average ReadExReq miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester1 93137.138995 # average ReadExReq miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester0 95989.518748 # average ReadExReq miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester1 95289.808064 # average ReadExReq miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_miss_latency::total 95093.378532 # average ReadExReq miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester0 96498.857574 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester1 93981.549814 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester0 95731.520468 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester1 95753.892003 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::total 95489.907286 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester0 96301.158642 # average overall miss latency
|
|
system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester1 93673.760115 # average overall miss latency
|
|
system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 95826.277247 # average overall miss latency
|
|
system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 95584.996632 # average overall miss latency
|
|
system.l2subsys0.cache1.demand_avg_miss_latency::total 95345.141859 # average overall miss latency
|
|
system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester0 96301.158642 # average overall miss latency
|
|
system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester1 93673.760115 # average overall miss latency
|
|
system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 95826.277247 # average overall miss latency
|
|
system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 95584.996632 # average overall miss latency
|
|
system.l2subsys0.cache1.overall_avg_miss_latency::total 95345.141859 # average overall miss latency
|
|
system.l2subsys0.cache1.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache1.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache1.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache1.writebacks::writebacks 45824 # number of writebacks
|
|
system.l2subsys0.cache1.writebacks::total 45824 # number of writebacks
|
|
system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester0 331 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester1 329 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester0 351 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester1 338 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache1.ReadExReq_mshr_hits::total 1349 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester0 639 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester1 567 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester0 568 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester1 602 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_hits::total 2376 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester0 970 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester1 896 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 919 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 940 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache1.demand_mshr_hits::total 3725 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester0 970 # number of overall MSHR hits
|
|
system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester1 896 # number of overall MSHR hits
|
|
system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 919 # number of overall MSHR hits
|
|
system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 940 # number of overall MSHR hits
|
|
system.l2subsys0.cache1.overall_mshr_hits::total 3725 # number of overall MSHR hits
|
|
system.l2subsys0.cache1.CleanEvict_mshr_misses::writebacks 42174 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache1.CleanEvict_mshr_misses::total 42174 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester0 3496 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester1 3545 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester0 3229 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester1 3694 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_misses::total 13964 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys0.tester0 16202 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys0.tester1 16355 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys1.tester0 16424 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys1.tester1 16626 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_misses::total 65607 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester0 28169 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester1 28521 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester0 28331 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester1 29047 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_misses::total 114068 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester0 44371 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester1 44876 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 44755 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 45673 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache1.demand_mshr_misses::total 179675 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache1.overall_mshr_misses::l0subsys0.tester0 44371 # number of overall MSHR misses
|
|
system.l2subsys0.cache1.overall_mshr_misses::l0subsys0.tester1 44876 # number of overall MSHR misses
|
|
system.l2subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 44755 # number of overall MSHR misses
|
|
system.l2subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 45673 # number of overall MSHR misses
|
|
system.l2subsys0.cache1.overall_mshr_misses::total 179675 # number of overall MSHR misses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys0.tester0 81694095 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys0.tester1 82958571 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys1.tester0 75782149 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys1.tester1 87927408 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::total 328362223 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester0 1414482686 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester1 1379942377 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester0 1435894366 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester1 1440517955 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::total 5670837384 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester0 2482055887 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester1 2433508746 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester0 2468466034 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester1 2532799653 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::total 9916830320 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache1.demand_mshr_miss_latency::total 15587667704 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache1.overall_mshr_miss_latency::total 15587667704 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester0 0.954148 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester1 0.966994 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester0 0.957876 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester1 0.958485 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::total 0.959395 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester0 0.977496 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester1 0.977410 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester0 0.976863 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester1 0.978173 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::total 0.977487 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester0 0.955076 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester1 0.959657 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester0 0.956321 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester1 0.956122 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::total 0.956794 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache1.demand_mshr_miss_rate::total 0.964248 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache1.overall_mshr_miss_rate::total 0.964248 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester0 23367.876144 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester1 23401.571509 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester0 23469.231651 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester1 23802.763400 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::total 23514.911415 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester0 87302.967905 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester1 84374.342831 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester0 87426.593156 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester1 86642.484963 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::total 86436.468426 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester0 88113.028045 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester1 85323.401914 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester0 87129.505983 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester1 87196.600441 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::total 86937.881965 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.demand_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency
|
|
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache2.tags.replacements 148896 # number of replacements
|
|
system.l2subsys0.cache2.tags.tagsinuse 1523.034958 # Cycle average of tags in use
|
|
system.l2subsys0.cache2.tags.total_refs 81242 # Total number of references to valid blocks.
|
|
system.l2subsys0.cache2.tags.sampled_refs 150425 # Sample count of references to valid blocks.
|
|
system.l2subsys0.cache2.tags.avg_refs 0.540083 # Average number of references to valid blocks.
|
|
system.l2subsys0.cache2.tags.warmup_cycle 259670000 # Cycle when the warmup percentage was hit.
|
|
system.l2subsys0.cache2.tags.occ_blocks::writebacks 189.526445 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester0 325.843379 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester1 331.240676 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester0 338.598926 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester1 337.825532 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache2.tags.occ_percent::writebacks 0.123390 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester0 0.212138 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester1 0.215651 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester0 0.220442 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester1 0.219938 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_percent::total 0.991559 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache2.tags.occ_task_id_blocks::1024 1529 # Occupied blocks per task id
|
|
system.l2subsys0.cache2.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id
|
|
system.l2subsys0.cache2.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id
|
|
system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
|
|
system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.995443 # Percentage of cache occupancy per task id
|
|
system.l2subsys0.cache2.tags.tag_accesses 4107279 # Number of tag accesses
|
|
system.l2subsys0.cache2.tags.data_accesses 4107279 # Number of data accesses
|
|
system.l2subsys0.cache2.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45595 # number of WritebackDirty hits
|
|
system.l2subsys0.cache2.WritebackDirty_hits::total 45595 # number of WritebackDirty hits
|
|
system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester0 140 # number of UpgradeReq hits
|
|
system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester1 149 # number of UpgradeReq hits
|
|
system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester0 120 # number of UpgradeReq hits
|
|
system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester1 184 # number of UpgradeReq hits
|
|
system.l2subsys0.cache2.UpgradeReq_hits::total 593 # number of UpgradeReq hits
|
|
system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 45 # number of ReadExReq hits
|
|
system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester1 36 # number of ReadExReq hits
|
|
system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester0 49 # number of ReadExReq hits
|
|
system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester1 30 # number of ReadExReq hits
|
|
system.l2subsys0.cache2.ReadExReq_hits::total 160 # number of ReadExReq hits
|
|
system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester0 644 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester1 713 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester0 722 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester1 725 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache2.ReadSharedReq_hits::total 2804 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache2.demand_hits::l0subsys2.tester0 689 # number of demand (read+write) hits
|
|
system.l2subsys0.cache2.demand_hits::l0subsys2.tester1 749 # number of demand (read+write) hits
|
|
system.l2subsys0.cache2.demand_hits::l0subsys3.tester0 771 # number of demand (read+write) hits
|
|
system.l2subsys0.cache2.demand_hits::l0subsys3.tester1 755 # number of demand (read+write) hits
|
|
system.l2subsys0.cache2.demand_hits::total 2964 # number of demand (read+write) hits
|
|
system.l2subsys0.cache2.overall_hits::l0subsys2.tester0 689 # number of overall hits
|
|
system.l2subsys0.cache2.overall_hits::l0subsys2.tester1 749 # number of overall hits
|
|
system.l2subsys0.cache2.overall_hits::l0subsys3.tester0 771 # number of overall hits
|
|
system.l2subsys0.cache2.overall_hits::l0subsys3.tester1 755 # number of overall hits
|
|
system.l2subsys0.cache2.overall_hits::total 2964 # number of overall hits
|
|
system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester0 3731 # number of UpgradeReq misses
|
|
system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester1 3588 # number of UpgradeReq misses
|
|
system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester0 3374 # number of UpgradeReq misses
|
|
system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester1 3500 # number of UpgradeReq misses
|
|
system.l2subsys0.cache2.UpgradeReq_misses::total 14193 # number of UpgradeReq misses
|
|
system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester0 16480 # number of ReadExReq misses
|
|
system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester1 16325 # number of ReadExReq misses
|
|
system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester0 16664 # number of ReadExReq misses
|
|
system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester1 16716 # number of ReadExReq misses
|
|
system.l2subsys0.cache2.ReadExReq_misses::total 66185 # number of ReadExReq misses
|
|
system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester0 28695 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester1 28471 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester0 29046 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester1 28633 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache2.ReadSharedReq_misses::total 114845 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache2.demand_misses::l0subsys2.tester0 45175 # number of demand (read+write) misses
|
|
system.l2subsys0.cache2.demand_misses::l0subsys2.tester1 44796 # number of demand (read+write) misses
|
|
system.l2subsys0.cache2.demand_misses::l0subsys3.tester0 45710 # number of demand (read+write) misses
|
|
system.l2subsys0.cache2.demand_misses::l0subsys3.tester1 45349 # number of demand (read+write) misses
|
|
system.l2subsys0.cache2.demand_misses::total 181030 # number of demand (read+write) misses
|
|
system.l2subsys0.cache2.overall_misses::l0subsys2.tester0 45175 # number of overall misses
|
|
system.l2subsys0.cache2.overall_misses::l0subsys2.tester1 44796 # number of overall misses
|
|
system.l2subsys0.cache2.overall_misses::l0subsys3.tester0 45710 # number of overall misses
|
|
system.l2subsys0.cache2.overall_misses::l0subsys3.tester1 45349 # number of overall misses
|
|
system.l2subsys0.cache2.overall_misses::total 181030 # number of overall misses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester0 121091693 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester1 118634700 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester0 110743355 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester1 115936209 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_miss_latency::total 466405957 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester0 1562139697 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester1 1549554832 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester0 1596782082 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester1 1559906979 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_miss_latency::total 6268383590 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester0 2730087572 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester1 2753356756 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester0 2770847888 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester1 2694786136 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_latency::total 10949078352 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester0 4292227269 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester1 4302911588 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester0 4367629970 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester1 4254693115 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache2.demand_miss_latency::total 17217461942 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester0 4292227269 # number of overall miss cycles
|
|
system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester1 4302911588 # number of overall miss cycles
|
|
system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester0 4367629970 # number of overall miss cycles
|
|
system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester1 4254693115 # number of overall miss cycles
|
|
system.l2subsys0.cache2.overall_miss_latency::total 17217461942 # number of overall miss cycles
|
|
system.l2subsys0.cache2.WritebackDirty_accesses::writebacks 45595 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache2.WritebackDirty_accesses::total 45595 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester0 3871 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester1 3737 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester0 3494 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester1 3684 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.UpgradeReq_accesses::total 14786 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester0 16525 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester1 16361 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester0 16713 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester1 16746 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadExReq_accesses::total 66345 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester0 29339 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester1 29184 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester0 29768 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester1 29358 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.ReadSharedReq_accesses::total 117649 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache2.demand_accesses::l0subsys2.tester0 45864 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache2.demand_accesses::l0subsys2.tester1 45545 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache2.demand_accesses::l0subsys3.tester0 46481 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache2.demand_accesses::l0subsys3.tester1 46104 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache2.demand_accesses::total 183994 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache2.overall_accesses::l0subsys2.tester0 45864 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache2.overall_accesses::l0subsys2.tester1 45545 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache2.overall_accesses::l0subsys3.tester0 46481 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache2.overall_accesses::l0subsys3.tester1 46104 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache2.overall_accesses::total 183994 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester0 0.963834 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester1 0.960128 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester0 0.965655 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester1 0.950054 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_miss_rate::total 0.959894 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester0 0.997277 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester1 0.997800 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester0 0.997068 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester1 0.998209 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_miss_rate::total 0.997588 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester0 0.978050 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester1 0.975569 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester0 0.975746 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester1 0.975305 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_miss_rate::total 0.976166 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester0 0.984977 # miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester1 0.983555 # miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester0 0.983413 # miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester1 0.983624 # miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_miss_rate::total 0.983891 # miss rate for demand accesses
|
|
system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester0 0.984977 # miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester1 0.983555 # miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester0 0.983413 # miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester1 0.983624 # miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_miss_rate::total 0.983891 # miss rate for overall accesses
|
|
system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester0 32455.559635 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester1 33064.297659 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester0 32822.571132 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester1 33124.631143 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::total 32861.689354 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester0 94790.030158 # average ReadExReq miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester1 94919.132129 # average ReadExReq miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester0 95822.256481 # average ReadExReq miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester1 93318.196877 # average ReadExReq miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_miss_latency::total 94710.033845 # average ReadExReq miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester0 95141.577696 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester1 96707.413017 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester0 95395.162432 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester1 94114.697587 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::total 95337.875850 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency
|
|
system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency
|
|
system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency
|
|
system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency
|
|
system.l2subsys0.cache2.demand_avg_miss_latency::total 95108.335315 # average overall miss latency
|
|
system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency
|
|
system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency
|
|
system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency
|
|
system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency
|
|
system.l2subsys0.cache2.overall_avg_miss_latency::total 95108.335315 # average overall miss latency
|
|
system.l2subsys0.cache2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache2.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache2.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache2.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache2.writebacks::writebacks 44893 # number of writebacks
|
|
system.l2subsys0.cache2.writebacks::total 44893 # number of writebacks
|
|
system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester0 353 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester1 327 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester0 327 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester1 345 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache2.ReadExReq_mshr_hits::total 1352 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester0 566 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester1 596 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester0 556 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester1 587 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_hits::total 2305 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester0 919 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester1 923 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester0 883 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester1 932 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache2.demand_mshr_hits::total 3657 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester0 919 # number of overall MSHR hits
|
|
system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester1 923 # number of overall MSHR hits
|
|
system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester0 883 # number of overall MSHR hits
|
|
system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester1 932 # number of overall MSHR hits
|
|
system.l2subsys0.cache2.overall_mshr_hits::total 3657 # number of overall MSHR hits
|
|
system.l2subsys0.cache2.CleanEvict_mshr_misses::writebacks 41439 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache2.CleanEvict_mshr_misses::total 41439 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester0 3731 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester1 3588 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester0 3374 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester1 3500 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_misses::total 14193 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester0 16127 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester1 15998 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester0 16337 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester1 16371 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_misses::total 64833 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester0 28129 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester1 27875 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester0 28490 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester1 28046 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_misses::total 112540 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester0 44256 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester1 43873 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester0 44827 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester1 44417 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache2.demand_mshr_misses::total 177373 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester0 44256 # number of overall MSHR misses
|
|
system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester1 43873 # number of overall MSHR misses
|
|
system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester0 44827 # number of overall MSHR misses
|
|
system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester1 44417 # number of overall MSHR misses
|
|
system.l2subsys0.cache2.overall_mshr_misses::total 177373 # number of overall MSHR misses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester0 86821804 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester1 85216922 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester0 79514942 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester1 83404063 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::total 334957731 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester0 1390062688 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester1 1380024742 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester0 1423675349 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester1 1385907063 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::total 5579669842 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester0 2433916719 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester1 2458901936 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester0 2472187719 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester1 2398872655 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::total 9763879029 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache2.demand_mshr_miss_latency::total 15343548871 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache2.overall_mshr_miss_latency::total 15343548871 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester0 0.963834 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester1 0.960128 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester0 0.965655 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester1 0.950054 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::total 0.959894 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester0 0.975915 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester1 0.977813 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester0 0.977503 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester1 0.977607 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::total 0.977210 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester0 0.958758 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester1 0.955147 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester0 0.957068 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester1 0.955310 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::total 0.956574 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache2.demand_mshr_miss_rate::total 0.964015 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache2.overall_mshr_miss_rate::total 0.964015 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester0 23270.384347 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester1 23750.535674 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester0 23566.965619 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester1 23829.732286 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::total 23600.206510 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester0 86194.747194 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester1 86262.329166 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester0 87144.233886 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester1 84656.225215 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::total 86062.188114 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester0 86526.955064 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester1 88211.728646 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester0 86773.875711 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester1 85533.504065 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::total 86759.188102 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.demand_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency
|
|
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache3.tags.replacements 154799 # number of replacements
|
|
system.l2subsys0.cache3.tags.tagsinuse 1523.428503 # Cycle average of tags in use
|
|
system.l2subsys0.cache3.tags.total_refs 83314 # Total number of references to valid blocks.
|
|
system.l2subsys0.cache3.tags.sampled_refs 156330 # Sample count of references to valid blocks.
|
|
system.l2subsys0.cache3.tags.avg_refs 0.532937 # Average number of references to valid blocks.
|
|
system.l2subsys0.cache3.tags.warmup_cycle 238966000 # Cycle when the warmup percentage was hit.
|
|
system.l2subsys0.cache3.tags.occ_blocks::writebacks 188.347514 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester0 343.217725 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester1 332.812126 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester0 334.052084 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester1 324.999055 # Average occupied blocks per requestor
|
|
system.l2subsys0.cache3.tags.occ_percent::writebacks 0.122622 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester0 0.223449 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester1 0.216675 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester0 0.217482 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester1 0.211588 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_percent::total 0.991815 # Average percentage of cache occupancy
|
|
system.l2subsys0.cache3.tags.occ_task_id_blocks::1024 1531 # Occupied blocks per task id
|
|
system.l2subsys0.cache3.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
|
|
system.l2subsys0.cache3.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id
|
|
system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
|
|
system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.996745 # Percentage of cache occupancy per task id
|
|
system.l2subsys0.cache3.tags.tag_accesses 4224919 # Number of tag accesses
|
|
system.l2subsys0.cache3.tags.data_accesses 4224919 # Number of data accesses
|
|
system.l2subsys0.cache3.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.cache3.WritebackDirty_hits::writebacks 46868 # number of WritebackDirty hits
|
|
system.l2subsys0.cache3.WritebackDirty_hits::total 46868 # number of WritebackDirty hits
|
|
system.l2subsys0.cache3.UpgradeReq_hits::l0subsys4.tester0 165 # number of UpgradeReq hits
|
|
system.l2subsys0.cache3.UpgradeReq_hits::l0subsys4.tester1 191 # number of UpgradeReq hits
|
|
system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester0 147 # number of UpgradeReq hits
|
|
system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester1 196 # number of UpgradeReq hits
|
|
system.l2subsys0.cache3.UpgradeReq_hits::total 699 # number of UpgradeReq hits
|
|
system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 40 # number of ReadExReq hits
|
|
system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester1 33 # number of ReadExReq hits
|
|
system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester0 37 # number of ReadExReq hits
|
|
system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester1 40 # number of ReadExReq hits
|
|
system.l2subsys0.cache3.ReadExReq_hits::total 150 # number of ReadExReq hits
|
|
system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester0 559 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester1 814 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester0 645 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester1 658 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache3.ReadSharedReq_hits::total 2676 # number of ReadSharedReq hits
|
|
system.l2subsys0.cache3.demand_hits::l0subsys4.tester0 599 # number of demand (read+write) hits
|
|
system.l2subsys0.cache3.demand_hits::l0subsys4.tester1 847 # number of demand (read+write) hits
|
|
system.l2subsys0.cache3.demand_hits::l0subsys5.tester0 682 # number of demand (read+write) hits
|
|
system.l2subsys0.cache3.demand_hits::l0subsys5.tester1 698 # number of demand (read+write) hits
|
|
system.l2subsys0.cache3.demand_hits::total 2826 # number of demand (read+write) hits
|
|
system.l2subsys0.cache3.overall_hits::l0subsys4.tester0 599 # number of overall hits
|
|
system.l2subsys0.cache3.overall_hits::l0subsys4.tester1 847 # number of overall hits
|
|
system.l2subsys0.cache3.overall_hits::l0subsys5.tester0 682 # number of overall hits
|
|
system.l2subsys0.cache3.overall_hits::l0subsys5.tester1 698 # number of overall hits
|
|
system.l2subsys0.cache3.overall_hits::total 2826 # number of overall hits
|
|
system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester0 3395 # number of UpgradeReq misses
|
|
system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester1 3421 # number of UpgradeReq misses
|
|
system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester0 3449 # number of UpgradeReq misses
|
|
system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester1 3509 # number of UpgradeReq misses
|
|
system.l2subsys0.cache3.UpgradeReq_misses::total 13774 # number of UpgradeReq misses
|
|
system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester0 16336 # number of ReadExReq misses
|
|
system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester1 17077 # number of ReadExReq misses
|
|
system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester0 17011 # number of ReadExReq misses
|
|
system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester1 16732 # number of ReadExReq misses
|
|
system.l2subsys0.cache3.ReadExReq_misses::total 67156 # number of ReadExReq misses
|
|
system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester0 29044 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester1 29836 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester0 30115 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester1 29435 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache3.ReadSharedReq_misses::total 118430 # number of ReadSharedReq misses
|
|
system.l2subsys0.cache3.demand_misses::l0subsys4.tester0 45380 # number of demand (read+write) misses
|
|
system.l2subsys0.cache3.demand_misses::l0subsys4.tester1 46913 # number of demand (read+write) misses
|
|
system.l2subsys0.cache3.demand_misses::l0subsys5.tester0 47126 # number of demand (read+write) misses
|
|
system.l2subsys0.cache3.demand_misses::l0subsys5.tester1 46167 # number of demand (read+write) misses
|
|
system.l2subsys0.cache3.demand_misses::total 185586 # number of demand (read+write) misses
|
|
system.l2subsys0.cache3.overall_misses::l0subsys4.tester0 45380 # number of overall misses
|
|
system.l2subsys0.cache3.overall_misses::l0subsys4.tester1 46913 # number of overall misses
|
|
system.l2subsys0.cache3.overall_misses::l0subsys5.tester0 47126 # number of overall misses
|
|
system.l2subsys0.cache3.overall_misses::l0subsys5.tester1 46167 # number of overall misses
|
|
system.l2subsys0.cache3.overall_misses::total 185586 # number of overall misses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester0 113966013 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester1 112016969 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester0 112091322 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester1 114062531 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_miss_latency::total 452136835 # number of UpgradeReq miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester0 1573749171 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester1 1609992551 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester0 1612917211 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester1 1594343846 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_miss_latency::total 6391002779 # number of ReadExReq miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester0 2825020785 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester1 2832936908 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester0 2869238005 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester1 2817936974 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_latency::total 11345132672 # number of ReadSharedReq miss cycles
|
|
system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester0 4398769956 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester1 4442929459 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester0 4482155216 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester1 4412280820 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache3.demand_miss_latency::total 17736135451 # number of demand (read+write) miss cycles
|
|
system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester0 4398769956 # number of overall miss cycles
|
|
system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester1 4442929459 # number of overall miss cycles
|
|
system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester0 4482155216 # number of overall miss cycles
|
|
system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester1 4412280820 # number of overall miss cycles
|
|
system.l2subsys0.cache3.overall_miss_latency::total 17736135451 # number of overall miss cycles
|
|
system.l2subsys0.cache3.WritebackDirty_accesses::writebacks 46868 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache3.WritebackDirty_accesses::total 46868 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester0 3560 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester1 3612 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester0 3596 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester1 3705 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.UpgradeReq_accesses::total 14473 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester0 16376 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester1 17110 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester0 17048 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester1 16772 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadExReq_accesses::total 67306 # number of ReadExReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester0 29603 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester1 30650 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester0 30760 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester1 30093 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.ReadSharedReq_accesses::total 121106 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2subsys0.cache3.demand_accesses::l0subsys4.tester0 45979 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache3.demand_accesses::l0subsys4.tester1 47760 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache3.demand_accesses::l0subsys5.tester0 47808 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache3.demand_accesses::l0subsys5.tester1 46865 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache3.demand_accesses::total 188412 # number of demand (read+write) accesses
|
|
system.l2subsys0.cache3.overall_accesses::l0subsys4.tester0 45979 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache3.overall_accesses::l0subsys4.tester1 47760 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache3.overall_accesses::l0subsys5.tester0 47808 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache3.overall_accesses::l0subsys5.tester1 46865 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache3.overall_accesses::total 188412 # number of overall (read+write) accesses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester0 0.953652 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester1 0.947121 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester0 0.959121 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester1 0.947099 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_miss_rate::total 0.951703 # miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester0 0.997557 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester1 0.998071 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester0 0.997830 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester1 0.997615 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_miss_rate::total 0.997771 # miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester0 0.981117 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester1 0.973442 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester0 0.979031 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester1 0.978134 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_miss_rate::total 0.977904 # miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester0 0.986972 # miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester1 0.982265 # miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester0 0.985735 # miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester1 0.985106 # miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_miss_rate::total 0.985001 # miss rate for demand accesses
|
|
system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester0 0.986972 # miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester1 0.982265 # miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester0 0.985735 # miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester1 0.985106 # miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_miss_rate::total 0.985001 # miss rate for overall accesses
|
|
system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester0 33568.781443 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester1 32743.925460 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester0 32499.658452 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester1 32505.708464 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::total 32825.383694 # average UpgradeReq miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester0 96336.261692 # average ReadExReq miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester1 94278.418399 # average ReadExReq miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester0 94816.131386 # average ReadExReq miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester1 95287.105307 # average ReadExReq miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_miss_latency::total 95166.519432 # average ReadExReq miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester0 97266.932413 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester1 94950.291862 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester0 95276.042006 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester1 95734.227077 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::total 95796.104636 # average ReadSharedReq miss latency
|
|
system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester0 96931.907360 # average overall miss latency
|
|
system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester1 94705.720355 # average overall miss latency
|
|
system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester0 95110.028774 # average overall miss latency
|
|
system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester1 95572.179695 # average overall miss latency
|
|
system.l2subsys0.cache3.demand_avg_miss_latency::total 95568.283443 # average overall miss latency
|
|
system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester0 96931.907360 # average overall miss latency
|
|
system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester1 94705.720355 # average overall miss latency
|
|
system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester0 95110.028774 # average overall miss latency
|
|
system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester1 95572.179695 # average overall miss latency
|
|
system.l2subsys0.cache3.overall_avg_miss_latency::total 95568.283443 # average overall miss latency
|
|
system.l2subsys0.cache3.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache3.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache3.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache3.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2subsys0.cache3.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache3.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2subsys0.cache3.writebacks::writebacks 46143 # number of writebacks
|
|
system.l2subsys0.cache3.writebacks::total 46143 # number of writebacks
|
|
system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester0 265 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester1 407 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester0 288 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester1 291 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache3.ReadExReq_mshr_hits::total 1251 # number of ReadExReq MSHR hits
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester0 482 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester1 692 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester0 543 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester1 541 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_hits::total 2258 # number of ReadSharedReq MSHR hits
|
|
system.l2subsys0.cache3.demand_mshr_hits::l0subsys4.tester0 747 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache3.demand_mshr_hits::l0subsys4.tester1 1099 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache3.demand_mshr_hits::l0subsys5.tester0 831 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache3.demand_mshr_hits::l0subsys5.tester1 832 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache3.demand_mshr_hits::total 3509 # number of demand (read+write) MSHR hits
|
|
system.l2subsys0.cache3.overall_mshr_hits::l0subsys4.tester0 747 # number of overall MSHR hits
|
|
system.l2subsys0.cache3.overall_mshr_hits::l0subsys4.tester1 1099 # number of overall MSHR hits
|
|
system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester0 831 # number of overall MSHR hits
|
|
system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester1 832 # number of overall MSHR hits
|
|
system.l2subsys0.cache3.overall_mshr_hits::total 3509 # number of overall MSHR hits
|
|
system.l2subsys0.cache3.CleanEvict_mshr_misses::writebacks 43347 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache3.CleanEvict_mshr_misses::total 43347 # number of CleanEvict MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester0 3395 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester1 3421 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester0 3449 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester1 3509 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_misses::total 13774 # number of UpgradeReq MSHR misses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester0 16071 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester1 16670 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester0 16723 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester1 16441 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_misses::total 65905 # number of ReadExReq MSHR misses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester0 28562 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester1 29144 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester0 29572 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester1 28894 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_misses::total 116172 # number of ReadSharedReq MSHR misses
|
|
system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester0 44633 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester1 45814 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester0 46295 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester1 45335 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache3.demand_mshr_misses::total 182077 # number of demand (read+write) MSHR misses
|
|
system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester0 44633 # number of overall MSHR misses
|
|
system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester1 45814 # number of overall MSHR misses
|
|
system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester0 46295 # number of overall MSHR misses
|
|
system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester1 45335 # number of overall MSHR misses
|
|
system.l2subsys0.cache3.overall_mshr_misses::total 182077 # number of overall MSHR misses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester0 81963023 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester1 80624239 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester0 80607785 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester1 81849121 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::total 325044168 # number of UpgradeReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester0 1404906880 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester1 1431588330 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester0 1436530645 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester1 1420292171 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::total 5693318026 # number of ReadExReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester0 2526781875 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester1 2523316581 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester0 2559586993 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester1 2514975762 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::total 10124661211 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache3.demand_mshr_miss_latency::total 15817979237 # number of demand (read+write) MSHR miss cycles
|
|
system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache3.overall_mshr_miss_latency::total 15817979237 # number of overall MSHR miss cycles
|
|
system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester0 0.953652 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester1 0.947121 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester0 0.959121 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester1 0.947099 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::total 0.951703 # mshr miss rate for UpgradeReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester0 0.981375 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester1 0.974284 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester0 0.980936 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester1 0.980265 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::total 0.979185 # mshr miss rate for ReadExReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester0 0.964835 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester1 0.950865 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester0 0.961378 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester1 0.960157 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::total 0.959259 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache3.demand_mshr_miss_rate::total 0.966377 # mshr miss rate for demand accesses
|
|
system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache3.overall_mshr_miss_rate::total 0.966377 # mshr miss rate for overall accesses
|
|
system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester0 24142.274816 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester1 23567.447822 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester0 23371.349667 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester1 23325.483329 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::total 23598.385945 # average UpgradeReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester0 87418.759256 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester1 85878.124175 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester0 85901.491658 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester1 86387.213126 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::total 86386.738882 # average ReadExReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester0 88466.559590 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester1 86580.997152 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester0 86554.409340 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester1 87041.453658 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::total 87152.336286 # average ReadSharedReq mshr miss latency
|
|
system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.demand_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency
|
|
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency
|
|
system.l2subsys0.checkers.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.tester.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.tester.numPackets 67448 # Number of packets generated
|
|
system.l2subsys0.tester.numRetries 90 # Number of retries
|
|
system.l2subsys0.tester.retryTicks 3855703 # Time spent waiting due to back-pressure (ticks)
|
|
system.l2subsys0.xbar.snoop_filter.tot_requests 1069827 # Total number of requests made to the snoop filter.
|
|
system.l2subsys0.xbar.snoop_filter.hit_single_requests 521153 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.l2subsys0.xbar.snoop_filter.hit_multi_requests 129649 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.l2subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
|
|
system.l2subsys0.xbar.trans_dist::ReadResp 375461 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1760 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::WritebackDirty 148958 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::CleanEvict 268634 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::UpgradeReq 51775 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::UpgradeResp 28212 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::ReadExReq 223238 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::ReadExResp 218900 # Transaction distribution
|
|
system.l2subsys0.xbar.trans_dist::ReadSharedReq 377222 # Transaction distribution
|
|
system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache1.mem_side::system.physmem.port 454786 # Packet count per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache2.mem_side::system.physmem.port 447989 # Packet count per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache3.mem_side::system.physmem.port 462519 # Packet count per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache0.mem_side::system.physmem.port 127384 # Packet count per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_count::total 1492678 # Packet count per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache1.mem_side::system.physmem.port 11217984 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache2.mem_side::system.physmem.port 11005568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.port 11412416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port 2959808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.pkt_size::total 36595776 # Cumulative packet size per connected master and slave (bytes)
|
|
system.l2subsys0.xbar.snoops 210714 # Total snoops (count)
|
|
system.l2subsys0.xbar.snoopTraffic 11089280 # Total snoop traffic (bytes)
|
|
system.l2subsys0.xbar.snoop_fanout::samples 652235 # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::mean 0.520105 # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::stdev 0.790254 # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::0 420662 64.50% 64.50% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::1 138520 21.24% 85.73% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::2 78448 12.03% 97.76% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::3 14605 2.24% 100.00% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.l2subsys0.xbar.snoop_fanout::total 652235 # Request fanout histogram
|
|
system.l2subsys0.xbar.reqLayer0.occupancy 1600277509 # Layer occupancy (ticks)
|
|
system.l2subsys0.xbar.reqLayer0.utilization 16.0 # Layer utilization (%)
|
|
system.l2subsys0.xbar.respLayer0.occupancy 643009360 # Layer occupancy (ticks)
|
|
system.l2subsys0.xbar.respLayer0.utilization 6.4 # Layer utilization (%)
|
|
system.l2subsys0.xbar.respLayer1.occupancy 635003682 # Layer occupancy (ticks)
|
|
system.l2subsys0.xbar.respLayer1.utilization 6.4 # Layer utilization (%)
|
|
system.l2subsys0.xbar.respLayer2.occupancy 652235888 # Layer occupancy (ticks)
|
|
system.l2subsys0.xbar.respLayer2.utilization 6.5 # Layer utilization (%)
|
|
system.l2subsys0.xbar.respLayer3.occupancy 189829895 # Layer occupancy (ticks)
|
|
system.l2subsys0.xbar.respLayer3.utilization 1.9 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|