1724 lines
34 KiB
INI
1724 lines
34 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
eventq_index=0
|
|
full_system=true
|
|
sim_quantum=0
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
|
|
|
|
[system]
|
|
type=LinuxAlphaSystem
|
|
children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
|
|
boot_cpu_frequency=500
|
|
boot_osflags=root=/dev/hda1 console=ttyS0
|
|
cache_line_size=64
|
|
clk_domain=system.clk_domain
|
|
console=/arm/projectscratch/randd/systems/dist/binaries/console
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
exit_on_work_items=false
|
|
init_param=0
|
|
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
|
kernel_addr_check=true
|
|
load_addr_mask=1099511627775
|
|
load_offset=0
|
|
mem_mode=timing
|
|
mem_ranges=0:134217727
|
|
memories=system.physmem
|
|
mmap_using_noreserve=false
|
|
multi_thread=false
|
|
num_work_ids=16
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
|
|
power_model=Null
|
|
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
|
symbolfile=
|
|
system_rev=1024
|
|
system_type=34
|
|
thermal_components=
|
|
thermal_model=Null
|
|
work_begin_ckpt_count=0
|
|
work_begin_cpu_id_exit=-1
|
|
work_begin_exit_count=0
|
|
work_cpus_ckpt_count=0
|
|
work_end_ckpt_count=0
|
|
work_end_exit_count=0
|
|
work_item_id=-1
|
|
system_port=system.membus.slave[0]
|
|
|
|
[system.bridge]
|
|
type=Bridge
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
delay=50000
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
ranges=8796093022208:18446744073709551615
|
|
req_size=16
|
|
resp_size=16
|
|
master=system.iobus.slave[0]
|
|
slave=system.membus.master[0]
|
|
|
|
[system.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=1000
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.cpu]
|
|
type=DerivO3CPU
|
|
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
|
LFSTSize=1024
|
|
LQEntries=32
|
|
LSQCheckLoads=true
|
|
LSQDepCheckShift=4
|
|
SQEntries=32
|
|
SSITSize=1024
|
|
activity=0
|
|
backComSize=5
|
|
branchPred=system.cpu.branchPred
|
|
cachePorts=200
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
commitToDecodeDelay=1
|
|
commitToFetchDelay=1
|
|
commitToIEWDelay=1
|
|
commitToRenameDelay=1
|
|
commitWidth=8
|
|
cpu_id=0
|
|
decodeToFetchDelay=1
|
|
decodeToRenameDelay=1
|
|
decodeWidth=8
|
|
default_p_state=UNDEFINED
|
|
dispatchWidth=8
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu.dtb
|
|
eventq_index=0
|
|
fetchBufferSize=64
|
|
fetchQueueSize=32
|
|
fetchToDecodeDelay=1
|
|
fetchTrapLatency=1
|
|
fetchWidth=8
|
|
forwardComSize=5
|
|
fuPool=system.cpu.fuPool
|
|
function_trace=false
|
|
function_trace_start=0
|
|
iewToCommitDelay=1
|
|
iewToDecodeDelay=1
|
|
iewToFetchDelay=1
|
|
iewToRenameDelay=1
|
|
interrupts=system.cpu.interrupts
|
|
isa=system.cpu.isa
|
|
issueToExecuteDelay=1
|
|
issueWidth=8
|
|
itb=system.cpu.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
needsTSO=false
|
|
numIQEntries=64
|
|
numPhysCCRegs=0
|
|
numPhysFloatRegs=256
|
|
numPhysIntRegs=256
|
|
numROBEntries=192
|
|
numRobs=1
|
|
numThreads=1
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
profile=0
|
|
progress_interval=0
|
|
renameToDecodeDelay=1
|
|
renameToFetchDelay=1
|
|
renameToIEWDelay=2
|
|
renameToROBDelay=1
|
|
renameWidth=8
|
|
simpoint_start_insts=
|
|
smtCommitPolicy=RoundRobin
|
|
smtFetchPolicy=SingleThread
|
|
smtIQPolicy=Partitioned
|
|
smtIQThreshold=100
|
|
smtLSQPolicy=Partitioned
|
|
smtLSQThreshold=100
|
|
smtNumFetchingThreads=1
|
|
smtROBPolicy=Partitioned
|
|
smtROBThreshold=100
|
|
socket_id=0
|
|
squashWidth=8
|
|
store_set_clear_period=250000
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu.tracer
|
|
trapLatency=13
|
|
wbWidth=8
|
|
workload=
|
|
dcache_port=system.cpu.dcache.cpu_side
|
|
icache_port=system.cpu.icache.cpu_side
|
|
|
|
[system.cpu.branchPred]
|
|
type=TournamentBP
|
|
BTBEntries=4096
|
|
BTBTagSize=16
|
|
RASSize=16
|
|
choiceCtrBits=2
|
|
choicePredictorSize=8192
|
|
eventq_index=0
|
|
globalCtrBits=2
|
|
globalPredictorSize=8192
|
|
indirectHashGHR=true
|
|
indirectHashTargets=true
|
|
indirectPathLength=3
|
|
indirectSets=256
|
|
indirectTagSize=16
|
|
indirectWays=2
|
|
instShiftAmt=2
|
|
localCtrBits=2
|
|
localHistoryTableSize=2048
|
|
localPredictorSize=2048
|
|
numThreads=1
|
|
useIndirect=true
|
|
|
|
[system.cpu.dcache]
|
|
type=Cache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=4
|
|
clk_domain=system.cpu_clk_domain
|
|
clusivity=mostly_incl
|
|
default_p_state=UNDEFINED
|
|
demand_mshr_reserve=1
|
|
eventq_index=0
|
|
hit_latency=2
|
|
is_read_only=false
|
|
max_miss_count=0
|
|
mshrs=4
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=32768
|
|
system=system
|
|
tags=system.cpu.dcache.tags
|
|
tgts_per_mshr=20
|
|
write_buffers=8
|
|
writeback_clean=false
|
|
cpu_side=system.cpu.dcache_port
|
|
mem_side=system.cpu.toL2Bus.slave[1]
|
|
|
|
[system.cpu.dcache.tags]
|
|
type=LRU
|
|
assoc=4
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
hit_latency=2
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
sequential_access=false
|
|
size=32768
|
|
|
|
[system.cpu.dtb]
|
|
type=AlphaTLB
|
|
eventq_index=0
|
|
size=64
|
|
|
|
[system.cpu.fuPool]
|
|
type=FUPool
|
|
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
|
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
|
eventq_index=0
|
|
|
|
[system.cpu.fuPool.FUList0]
|
|
type=FUDesc
|
|
children=opList
|
|
count=6
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList0.opList
|
|
|
|
[system.cpu.fuPool.FUList0.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=IntAlu
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList1]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=2
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
|
|
|
[system.cpu.fuPool.FUList1.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=IntMult
|
|
opLat=3
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList1.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=IntDiv
|
|
opLat=20
|
|
pipelined=false
|
|
|
|
[system.cpu.fuPool.FUList2]
|
|
type=FUDesc
|
|
children=opList0 opList1 opList2
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
|
|
|
[system.cpu.fuPool.FUList2.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatAdd
|
|
opLat=2
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList2.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatCmp
|
|
opLat=2
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList2.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatCvt
|
|
opLat=2
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList3]
|
|
type=FUDesc
|
|
children=opList0 opList1 opList2
|
|
count=2
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
|
|
|
[system.cpu.fuPool.FUList3.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatMult
|
|
opLat=4
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList3.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatDiv
|
|
opLat=12
|
|
pipelined=false
|
|
|
|
[system.cpu.fuPool.FUList3.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=FloatSqrt
|
|
opLat=24
|
|
pipelined=false
|
|
|
|
[system.cpu.fuPool.FUList4]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList4.opList
|
|
|
|
[system.cpu.fuPool.FUList4.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=MemRead
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5]
|
|
type=FUDesc
|
|
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
|
|
|
[system.cpu.fuPool.FUList5.opList00]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdAdd
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList01]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdAddAcc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList02]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdAlu
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList03]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdCmp
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList04]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdCvt
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList05]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdMisc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList06]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdMult
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList07]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdMultAcc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList08]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdShift
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList09]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdShiftAcc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList10]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdSqrt
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList11]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatAdd
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList12]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatAlu
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList13]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatCmp
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList14]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatCvt
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList15]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatDiv
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList16]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatMisc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList17]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatMult
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList18]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatMultAcc
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList5.opList19]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=SimdFloatSqrt
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList6]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList6.opList
|
|
|
|
[system.cpu.fuPool.FUList6.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=MemWrite
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList7]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
|
|
|
[system.cpu.fuPool.FUList7.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=MemRead
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList7.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=MemWrite
|
|
opLat=1
|
|
pipelined=true
|
|
|
|
[system.cpu.fuPool.FUList8]
|
|
type=FUDesc
|
|
children=opList
|
|
count=1
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList8.opList
|
|
|
|
[system.cpu.fuPool.FUList8.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
opClass=IprAccess
|
|
opLat=3
|
|
pipelined=false
|
|
|
|
[system.cpu.icache]
|
|
type=Cache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=1
|
|
clk_domain=system.cpu_clk_domain
|
|
clusivity=mostly_incl
|
|
default_p_state=UNDEFINED
|
|
demand_mshr_reserve=1
|
|
eventq_index=0
|
|
hit_latency=2
|
|
is_read_only=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=32768
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
write_buffers=8
|
|
writeback_clean=true
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=1
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
hit_latency=2
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
sequential_access=false
|
|
size=32768
|
|
|
|
[system.cpu.interrupts]
|
|
type=AlphaInterrupts
|
|
eventq_index=0
|
|
|
|
[system.cpu.isa]
|
|
type=AlphaISA
|
|
eventq_index=0
|
|
system=system
|
|
|
|
[system.cpu.itb]
|
|
type=AlphaTLB
|
|
eventq_index=0
|
|
size=48
|
|
|
|
[system.cpu.l2cache]
|
|
type=Cache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
clusivity=mostly_incl
|
|
default_p_state=UNDEFINED
|
|
demand_mshr_reserve=1
|
|
eventq_index=0
|
|
hit_latency=20
|
|
is_read_only=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
sequential_access=false
|
|
size=4194304
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
write_buffers=8
|
|
writeback_clean=false
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
hit_latency=20
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
sequential_access=false
|
|
size=4194304
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentXBar
|
|
children=snoop_filter
|
|
clk_domain=system.cpu_clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
forward_latency=0
|
|
frontend_latency=1
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
point_of_coherency=false
|
|
power_model=Null
|
|
response_latency=1
|
|
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
|
snoop_response_latency=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|
|
|
[system.cpu.toL2Bus.snoop_filter]
|
|
type=SnoopFilter
|
|
eventq_index=0
|
|
lookup_latency=0
|
|
max_capacity=8388608
|
|
system=system
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.disk0]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.disk0.image
|
|
|
|
[system.disk0.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.disk0.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.disk0.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
|
read_only=true
|
|
|
|
[system.disk2]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.disk2.image
|
|
|
|
[system.disk2.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.disk2.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.disk2.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
|
|
read_only=true
|
|
|
|
[system.dvfs_handler]
|
|
type=DVFSHandler
|
|
domains=
|
|
enable=false
|
|
eventq_index=0
|
|
sys_clk_domain=system.clk_domain
|
|
transition_latency=100000000
|
|
|
|
[system.intrctrl]
|
|
type=IntrControl
|
|
eventq_index=0
|
|
sys=system
|
|
|
|
[system.iobus]
|
|
type=NoncoherentXBar
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
forward_latency=1
|
|
frontend_latency=2
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
response_latency=2
|
|
use_default_range=false
|
|
width=16
|
|
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
|
|
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
|
|
|
[system.iocache]
|
|
type=Cache
|
|
children=tags
|
|
addr_ranges=0:134217727
|
|
assoc=8
|
|
clk_domain=system.clk_domain
|
|
clusivity=mostly_incl
|
|
default_p_state=UNDEFINED
|
|
demand_mshr_reserve=1
|
|
eventq_index=0
|
|
hit_latency=50
|
|
is_read_only=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=50
|
|
sequential_access=false
|
|
size=1024
|
|
system=system
|
|
tags=system.iocache.tags
|
|
tgts_per_mshr=12
|
|
write_buffers=8
|
|
writeback_clean=false
|
|
cpu_side=system.iobus.master[27]
|
|
mem_side=system.membus.slave[2]
|
|
|
|
[system.iocache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
hit_latency=50
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
power_model=Null
|
|
sequential_access=false
|
|
size=1024
|
|
|
|
[system.membus]
|
|
type=CoherentXBar
|
|
children=badaddr_responder
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
forward_latency=4
|
|
frontend_latency=3
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
point_of_coherency=true
|
|
power_model=Null
|
|
response_latency=2
|
|
snoop_filter=Null
|
|
snoop_response_latency=4
|
|
system=system
|
|
use_default_range=false
|
|
width=16
|
|
default=system.membus.badaddr_responder.pio
|
|
master=system.bridge.slave system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|
|
|
[system.membus.badaddr_responder]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=0
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=true
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.membus.default
|
|
|
|
[system.physmem]
|
|
type=DRAMCtrl
|
|
IDD0=0.075000
|
|
IDD02=0.000000
|
|
IDD2N=0.050000
|
|
IDD2N2=0.000000
|
|
IDD2P0=0.000000
|
|
IDD2P02=0.000000
|
|
IDD2P1=0.000000
|
|
IDD2P12=0.000000
|
|
IDD3N=0.057000
|
|
IDD3N2=0.000000
|
|
IDD3P0=0.000000
|
|
IDD3P02=0.000000
|
|
IDD3P1=0.000000
|
|
IDD3P12=0.000000
|
|
IDD4R=0.187000
|
|
IDD4R2=0.000000
|
|
IDD4W=0.165000
|
|
IDD4W2=0.000000
|
|
IDD5=0.220000
|
|
IDD52=0.000000
|
|
IDD6=0.000000
|
|
IDD62=0.000000
|
|
VDD=1.500000
|
|
VDD2=0.000000
|
|
activation_limit=4
|
|
addr_mapping=RoRaBaCoCh
|
|
bank_groups_per_rank=0
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
default_p_state=UNDEFINED
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
device_size=536870912
|
|
devices_per_rank=8
|
|
dll=true
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
max_accesses_per_row=16
|
|
mem_sched_policy=frfcfs
|
|
min_writes_per_switch=16
|
|
null=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
page_policy=open_adaptive
|
|
power_model=Null
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCCD_L=0
|
|
tCK=1250
|
|
tCL=13750
|
|
tCS=2500
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=260000
|
|
tRP=13750
|
|
tRRD=6000
|
|
tRRD_L=0
|
|
tRTP=7500
|
|
tRTW=2500
|
|
tWR=15000
|
|
tWTR=7500
|
|
tXAW=30000
|
|
tXP=0
|
|
tXPDLL=0
|
|
tXS=0
|
|
tXSDLL=0
|
|
write_buffer_size=64
|
|
write_high_thresh_perc=85
|
|
write_low_thresh_perc=50
|
|
port=system.membus.master[1]
|
|
|
|
[system.simple_disk]
|
|
type=SimpleDisk
|
|
children=disk
|
|
disk=system.simple_disk.disk
|
|
eventq_index=0
|
|
system=system
|
|
|
|
[system.simple_disk.disk]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
|
read_only=true
|
|
|
|
[system.terminal]
|
|
type=Terminal
|
|
eventq_index=0
|
|
intr_control=system.intrctrl
|
|
number=0
|
|
output=true
|
|
port=3456
|
|
|
|
[system.tsunami]
|
|
type=Tsunami
|
|
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
|
|
eventq_index=0
|
|
intrctrl=system.intrctrl
|
|
system=system
|
|
|
|
[system.tsunami.backdoor]
|
|
type=AlphaBackdoor
|
|
clk_domain=system.clk_domain
|
|
cpu=system.cpu
|
|
default_p_state=UNDEFINED
|
|
disk=system.simple_disk
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804682956800
|
|
pio_latency=100000
|
|
platform=system.tsunami
|
|
power_model=Null
|
|
system=system
|
|
terminal=system.terminal
|
|
pio=system.iobus.master[24]
|
|
|
|
[system.tsunami.cchip]
|
|
type=TsunamiCChip
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8803072344064
|
|
pio_latency=100000
|
|
power_model=Null
|
|
system=system
|
|
tsunami=system.tsunami
|
|
pio=system.iobus.master[0]
|
|
|
|
[system.tsunami.ethernet]
|
|
type=NSGigE
|
|
BAR0=1
|
|
BAR0LegacyIO=false
|
|
BAR0Size=256
|
|
BAR1=0
|
|
BAR1LegacyIO=false
|
|
BAR1Size=4096
|
|
BAR2=0
|
|
BAR2LegacyIO=false
|
|
BAR2Size=0
|
|
BAR3=0
|
|
BAR3LegacyIO=false
|
|
BAR3Size=0
|
|
BAR4=0
|
|
BAR4LegacyIO=false
|
|
BAR4Size=0
|
|
BAR5=0
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=2
|
|
Command=0
|
|
DeviceID=34
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=30
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
LegacyIOBase=0
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=52
|
|
MinimumGrant=176
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=0
|
|
Revision=0
|
|
Status=656
|
|
SubClassCode=0
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=4107
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
default_p_state=UNDEFINED
|
|
dma_data_free=false
|
|
dma_desc_free=false
|
|
dma_no_allocate=true
|
|
dma_read_delay=0
|
|
dma_read_factor=0
|
|
dma_write_delay=0
|
|
dma_write_factor=0
|
|
eventq_index=0
|
|
hardware_address=00:90:00:00:00:01
|
|
host=system.tsunami.pchip
|
|
intr_delay=10000000
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pci_bus=0
|
|
pci_dev=1
|
|
pci_func=0
|
|
pio_latency=30000
|
|
power_model=Null
|
|
rss=false
|
|
rx_delay=1000000
|
|
rx_fifo_size=524288
|
|
rx_filter=true
|
|
rx_thread=false
|
|
system=system
|
|
tx_delay=1000000
|
|
tx_fifo_size=524288
|
|
tx_thread=false
|
|
dma=system.iobus.slave[2]
|
|
pio=system.iobus.master[26]
|
|
|
|
[system.tsunami.fake_OROM]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8796093677568
|
|
pio_latency=100000
|
|
pio_size=393216
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[8]
|
|
|
|
[system.tsunami.fake_ata0]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848432
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[19]
|
|
|
|
[system.tsunami.fake_ata1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848304
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[20]
|
|
|
|
[system.tsunami.fake_pnp_addr]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848569
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[9]
|
|
|
|
[system.tsunami.fake_pnp_read0]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848451
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[11]
|
|
|
|
[system.tsunami.fake_pnp_read1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848515
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[12]
|
|
|
|
[system.tsunami.fake_pnp_read2]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848579
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[13]
|
|
|
|
[system.tsunami.fake_pnp_read3]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848643
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[14]
|
|
|
|
[system.tsunami.fake_pnp_read4]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848707
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[15]
|
|
|
|
[system.tsunami.fake_pnp_read5]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848771
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[16]
|
|
|
|
[system.tsunami.fake_pnp_read6]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848835
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[17]
|
|
|
|
[system.tsunami.fake_pnp_read7]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848899
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[18]
|
|
|
|
[system.tsunami.fake_pnp_write]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615850617
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[10]
|
|
|
|
[system.tsunami.fake_ppc]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848891
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[7]
|
|
|
|
[system.tsunami.fake_sm_chip]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848816
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[2]
|
|
|
|
[system.tsunami.fake_uart1]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848696
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[3]
|
|
|
|
[system.tsunami.fake_uart2]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848936
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[4]
|
|
|
|
[system.tsunami.fake_uart3]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848680
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[5]
|
|
|
|
[system.tsunami.fake_uart4]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
fake_mem=false
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848944
|
|
pio_latency=100000
|
|
pio_size=8
|
|
power_model=Null
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[6]
|
|
|
|
[system.tsunami.fb]
|
|
type=BadDevice
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
devicename=FrameBuffer
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848912
|
|
pio_latency=100000
|
|
power_model=Null
|
|
system=system
|
|
pio=system.iobus.master[21]
|
|
|
|
[system.tsunami.ide]
|
|
type=IdeController
|
|
BAR0=1
|
|
BAR0LegacyIO=false
|
|
BAR0Size=8
|
|
BAR1=1
|
|
BAR1LegacyIO=false
|
|
BAR1Size=4
|
|
BAR2=1
|
|
BAR2LegacyIO=false
|
|
BAR2Size=8
|
|
BAR3=1
|
|
BAR3LegacyIO=false
|
|
BAR3Size=4
|
|
BAR4=1
|
|
BAR4LegacyIO=false
|
|
BAR4Size=16
|
|
BAR5=1
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=1
|
|
Command=0
|
|
DeviceID=28945
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=31
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
LegacyIOBase=0
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=0
|
|
MinimumGrant=0
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=133
|
|
Revision=0
|
|
Status=640
|
|
SubClassCode=1
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=32902
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
ctrl_offset=0
|
|
default_p_state=UNDEFINED
|
|
disks=system.disk0 system.disk2
|
|
eventq_index=0
|
|
host=system.tsunami.pchip
|
|
io_shift=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pci_bus=0
|
|
pci_dev=0
|
|
pci_func=0
|
|
pio_latency=30000
|
|
power_model=Null
|
|
system=system
|
|
dma=system.iobus.slave[1]
|
|
pio=system.iobus.master[25]
|
|
|
|
[system.tsunami.io]
|
|
type=TsunamiIO
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
frequency=976562500
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615847936
|
|
pio_latency=100000
|
|
power_model=Null
|
|
system=system
|
|
time=Thu Jan 1 00:00:00 2009
|
|
tsunami=system.tsunami
|
|
year_is_bcd=false
|
|
pio=system.iobus.master[22]
|
|
|
|
[system.tsunami.pchip]
|
|
type=TsunamiPChip
|
|
clk_domain=system.clk_domain
|
|
conf_base=8804649402368
|
|
conf_device_bits=8
|
|
conf_size=16777216
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pci_dma_base=0
|
|
pci_mem_base=8796093022208
|
|
pci_pio_base=8804615847936
|
|
pio_addr=8802535473152
|
|
pio_latency=100000
|
|
platform=system.tsunami
|
|
power_model=Null
|
|
system=system
|
|
tsunami=system.tsunami
|
|
pio=system.iobus.master[1]
|
|
|
|
[system.tsunami.uart]
|
|
type=Uart8250
|
|
clk_domain=system.clk_domain
|
|
default_p_state=UNDEFINED
|
|
eventq_index=0
|
|
p_state_clk_gate_bins=20
|
|
p_state_clk_gate_max=1000000000000
|
|
p_state_clk_gate_min=1000
|
|
pio_addr=8804615848952
|
|
pio_latency=100000
|
|
platform=system.tsunami
|
|
power_model=Null
|
|
system=system
|
|
terminal=system.terminal
|
|
pio=system.iobus.master[23]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|