7433d77fcf
This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py
449 lines
16 KiB
C++
449 lines
16 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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* Andreas Hansson
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*/
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#include <vector>
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/LLSC.hh"
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#include "debug/MemoryAccess.hh"
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#include "mem/abstract_mem.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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using namespace std;
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AbstractMemory::AbstractMemory(const Params *p) :
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MemObject(p), range(params()->range), pmemAddr(NULL),
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confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
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_system(NULL)
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{
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}
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void
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AbstractMemory::init()
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{
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assert(system());
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if (size() % _system->getPageBytes() != 0)
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panic("Memory Size not divisible by page size\n");
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}
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void
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AbstractMemory::setBackingStore(uint8_t* pmem_addr)
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{
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pmemAddr = pmem_addr;
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}
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void
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AbstractMemory::regStats()
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{
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using namespace Stats;
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assert(system());
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bytesRead
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.init(system()->maxMasters())
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.name(name() + ".bytes_read")
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.desc("Number of bytes read from this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bytesRead.subname(i, system()->getMasterName(i));
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}
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bytesInstRead
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.init(system()->maxMasters())
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.name(name() + ".bytes_inst_read")
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.desc("Number of instructions bytes read from this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bytesInstRead.subname(i, system()->getMasterName(i));
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}
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bytesWritten
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.init(system()->maxMasters())
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.name(name() + ".bytes_written")
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.desc("Number of bytes written to this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bytesWritten.subname(i, system()->getMasterName(i));
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}
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numReads
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.init(system()->maxMasters())
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.name(name() + ".num_reads")
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.desc("Number of read requests responded to by this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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numReads.subname(i, system()->getMasterName(i));
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}
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numWrites
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.init(system()->maxMasters())
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.name(name() + ".num_writes")
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.desc("Number of write requests responded to by this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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numWrites.subname(i, system()->getMasterName(i));
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}
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numOther
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.init(system()->maxMasters())
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.name(name() + ".num_other")
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.desc("Number of other requests responded to by this memory")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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numOther.subname(i, system()->getMasterName(i));
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}
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bwRead
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.name(name() + ".bw_read")
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.desc("Total read bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesRead)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bwRead.subname(i, system()->getMasterName(i));
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}
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bwInstRead
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.name(name() + ".bw_inst_read")
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.desc("Instruction read bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesInstRead)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bwInstRead.subname(i, system()->getMasterName(i));
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}
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bwWrite
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.name(name() + ".bw_write")
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.desc("Write bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesWritten)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bwWrite.subname(i, system()->getMasterName(i));
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}
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bwTotal
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.name(name() + ".bw_total")
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.desc("Total bandwidth to/from this memory (bytes/s)")
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.precision(0)
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.prereq(bwTotal)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system()->maxMasters(); i++) {
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bwTotal.subname(i, system()->getMasterName(i));
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}
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bwRead = bytesRead / simSeconds;
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bwInstRead = bytesInstRead / simSeconds;
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bwWrite = bytesWritten / simSeconds;
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bwTotal = (bytesRead + bytesWritten) / simSeconds;
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}
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AddrRange
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AbstractMemory::getAddrRange() const
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{
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return range;
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}
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// Add load-locked to tracking list. Should only be called if the
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// operation is a load and the LLSC flag is set.
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void
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AbstractMemory::trackLoadLocked(PacketPtr pkt)
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{
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Request *req = pkt->req;
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Addr paddr = LockedAddr::mask(req->getPaddr());
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// first we check if we already have a locked addr for this
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// xc. Since each xc only gets one, we just update the
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// existing record with the new address.
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list<LockedAddr>::iterator i;
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for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
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if (i->matchesContext(req)) {
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DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
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req->contextId(), paddr);
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i->addr = paddr;
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return;
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}
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}
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// no record for this xc: need to allocate a new one
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DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
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req->contextId(), paddr);
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lockedAddrList.push_front(LockedAddr(req));
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}
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// Called on *writes* only... both regular stores and
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// store-conditional operations. Check for conventional stores which
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// conflict with locked addresses, and for success/failure of store
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// conditionals.
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bool
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AbstractMemory::checkLockedAddrList(PacketPtr pkt)
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{
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Request *req = pkt->req;
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Addr paddr = LockedAddr::mask(req->getPaddr());
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bool isLLSC = pkt->isLLSC();
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// Initialize return value. Non-conditional stores always
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// succeed. Assume conditional stores will fail until proven
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// otherwise.
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bool allowStore = !isLLSC;
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// Iterate over list. Note that there could be multiple matching records,
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// as more than one context could have done a load locked to this location.
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// Only remove records when we succeed in finding a record for (xc, addr);
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// then, remove all records with this address. Failed store-conditionals do
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// not blow unrelated reservations.
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list<LockedAddr>::iterator i = lockedAddrList.begin();
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if (isLLSC) {
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while (i != lockedAddrList.end()) {
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if (i->addr == paddr && i->matchesContext(req)) {
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// it's a store conditional, and as far as the memory system can
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// tell, the requesting context's lock is still valid.
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DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
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req->contextId(), paddr);
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allowStore = true;
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break;
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}
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// If we didn't find a match, keep searching! Someone else may well
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// have a reservation on this line here but we may find ours in just
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// a little while.
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i++;
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}
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req->setExtraData(allowStore ? 1 : 0);
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}
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// LLSCs that succeeded AND non-LLSC stores both fall into here:
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if (allowStore) {
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// We write address paddr. However, there may be several entries with a
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// reservation on this address (for other contextIds) and they must all
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// be removed.
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i = lockedAddrList.begin();
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while (i != lockedAddrList.end()) {
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if (i->addr == paddr) {
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DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
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i->contextId, paddr);
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// For ARM, a spinlock would typically include a Wait
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// For Event (WFE) to conserve energy. The ARMv8
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// architecture specifies that an event is
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// automatically generated when clearing the exclusive
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// monitor to wake up the processor in WFE.
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ThreadContext* ctx = system()->getThreadContext(i->contextId);
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ctx->getCpuPtr()->wakeup(ctx->threadId());
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i = lockedAddrList.erase(i);
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} else {
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i++;
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}
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}
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}
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return allowStore;
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}
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#if TRACING_ON
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#define CASE(A, T) \
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case sizeof(T): \
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DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \
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"0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\
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pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \
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pkt->req->isUncacheable() ? 'U' : 'C'); \
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break
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#define TRACE_PACKET(A) \
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do { \
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switch (pkt->getSize()) { \
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CASE(A, uint64_t); \
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CASE(A, uint32_t); \
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CASE(A, uint16_t); \
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CASE(A, uint8_t); \
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default: \
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DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\
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A, system()->getMasterName(pkt->req->masterId()), \
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pkt->getSize(), pkt->getAddr(), \
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pkt->req->isUncacheable() ? 'U' : 'C'); \
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DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \
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} \
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} while (0)
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#else
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#define TRACE_PACKET(A)
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#endif
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void
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AbstractMemory::access(PacketPtr pkt)
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{
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if (pkt->memInhibitAsserted()) {
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DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
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pkt->getAddr());
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return;
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}
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if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
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DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
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pkt->getAddr());
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return;
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}
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assert(AddrRange(pkt->getAddr(),
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pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
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uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
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if (pkt->cmd == MemCmd::SwapReq) {
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std::vector<uint8_t> overwrite_val(pkt->getSize());
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uint64_t condition_val64;
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uint32_t condition_val32;
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if (!pmemAddr)
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panic("Swap only works if there is real memory (i.e. null=False)");
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bool overwrite_mem = true;
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// keep a copy of our possible write value, and copy what is at the
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// memory address into the packet
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std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(),
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pkt->getSize());
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std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
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if (pkt->req->isCondSwap()) {
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if (pkt->getSize() == sizeof(uint64_t)) {
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condition_val64 = pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
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sizeof(uint64_t));
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} else if (pkt->getSize() == sizeof(uint32_t)) {
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condition_val32 = (uint32_t)pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
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sizeof(uint32_t));
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} else
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panic("Invalid size for conditional read/write\n");
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}
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if (overwrite_mem)
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std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize());
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Read/Write");
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numOther[pkt->req->masterId()]++;
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} else if (pkt->isRead()) {
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assert(!pkt->isWrite());
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if (pkt->isLLSC()) {
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trackLoadLocked(pkt);
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}
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if (pmemAddr)
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memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
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TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
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numReads[pkt->req->masterId()]++;
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bytesRead[pkt->req->masterId()] += pkt->getSize();
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if (pkt->req->isInstFetch())
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bytesInstRead[pkt->req->masterId()] += pkt->getSize();
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} else if (pkt->isInvalidate()) {
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// no need to do anything
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// this clause is intentionally before the write clause: the only
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// transaction that is both a write and an invalidate is
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// WriteInvalidate, and for the sake of consistency, it does not
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// write to memory. in a cacheless system, there are no WriteInv's
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// because the Write -> WriteInvalidate rewrite happens in the cache.
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} else if (pkt->isWrite()) {
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if (writeOK(pkt)) {
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if (pmemAddr) {
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memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
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DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
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__func__, pkt->getSize(), pkt->getAddr());
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}
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Write");
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numWrites[pkt->req->masterId()]++;
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bytesWritten[pkt->req->masterId()] += pkt->getSize();
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}
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} else {
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panic("unimplemented");
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}
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if (pkt->needsResponse()) {
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pkt->makeResponse();
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}
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}
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void
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AbstractMemory::functionalAccess(PacketPtr pkt)
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{
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assert(AddrRange(pkt->getAddr(),
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pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
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uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
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if (pkt->isRead()) {
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if (pmemAddr)
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memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
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TRACE_PACKET("Read");
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pkt->makeResponse();
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} else if (pkt->isWrite()) {
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if (pmemAddr)
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memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
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TRACE_PACKET("Write");
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pkt->makeResponse();
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} else if (pkt->isPrint()) {
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Packet::PrintReqState *prs =
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dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
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assert(prs);
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// Need to call printLabels() explicitly since we're not going
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// through printObj().
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prs->printLabels();
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// Right now we just print the single byte at the specified address.
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ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
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} else {
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panic("AbstractMemory: unimplemented functional command %s",
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pkt->cmdString());
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}
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}
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