Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width ... This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.		2012-10-15 08:09:54 -04:00
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o3-timing	Stats: Update stats for new default L1-to-L2 bus clock and width	2012-10-15 08:09:54 -04:00
simple-atomic	x86 Regressions: Update stats due to register predication	2012-09-11 09:34:40 -05:00
simple-timing	Stats: Update stats for new default L1-to-L2 bus clock and width	2012-10-15 08:09:54 -04:00
simple-timing-ruby	Regression Tests: Update statistics	2012-10-02 14:35:46 -05:00