sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/dev
History
Ali Saidi 8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00
..
alpha_access.h Get rid of the xc from the alphaAccess/alphaConsole backdoor device. 2006-02-23 14:50:16 -05:00
alpha_console.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
alpha_console.hh updates for newmem 2006-04-10 14:14:06 -04:00
baddev.cc fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
baddev.hh updates for newmem 2006-04-10 14:14:06 -04:00
disk_image.cc byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. 2006-02-03 00:16:44 -05:00
disk_image.hh Many files: 2005-06-05 05:16:00 -04:00
etherbus.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherbus.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherdump.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherdump.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherint.cc Many files: 2005-06-05 05:16:00 -04:00
etherint.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherlink.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherlink.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherpkt.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
etherpkt.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ethertap.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ethertap.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ide_atareg.h Fixes for cygwin compile. 2005-06-30 00:42:27 -04:00
ide_ctrl.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ide_ctrl.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
ide_disk.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ide_disk.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
ide_wdcreg.h Fix doxgyen comments 2005-06-04 23:56:53 -04:00
io_device.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
io_device.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
isa_fake.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
isa_fake.hh updates for newmem 2006-04-10 14:14:06 -04:00
ns_gige.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ns_gige.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
ns_gige_reg.h Ethernet devices have an RSS option to tell the driver to 2006-03-03 14:17:48 -05:00
pciconfigall.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
pciconfigall.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
pcidev.cc make ide disk work for newmem 2006-04-20 17:14:30 -04:00
pcidev.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
pcireg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
pitreg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
pktfifo.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
pktfifo.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
platform.cc fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
platform.hh fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
rtcreg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
simconsole.cc fixes for newmem 2006-04-06 14:57:51 -04:00
simconsole.hh Many files: 2005-06-05 05:16:00 -04:00
simple_disk.cc fixes for newmem 2006-04-06 14:57:51 -04:00
simple_disk.hh fixes for newmem 2006-04-06 14:57:51 -04:00
sinic.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
sinic.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
sinicreg.hh Ethernet devices have an RSS option to tell the driver to 2006-03-03 14:17:48 -05:00
tsunami.cc fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
tsunami.hh fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
tsunami_cchip.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
tsunami_cchip.hh added unimp faults 2006-04-06 18:04:49 -04:00
tsunami_io.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
tsunami_io.hh fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
tsunami_pchip.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
tsunami_pchip.hh fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
tsunamireg.h Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5 2005-08-15 17:17:17 -04:00
uart.cc fixes for newmem 2006-04-06 14:57:51 -04:00
uart.hh fixes for newmem 2006-04-06 14:57:51 -04:00
uart8250.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
uart8250.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00