70b35bab57
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
265 lines
7.5 KiB
C++
265 lines
7.5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "arch/alpha/vtophys.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional/physical.hh"
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using namespace std;
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using namespace AlphaISA;
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AlphaISA::PageTableEntry
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kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
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{
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Addr level1_pte = ptbr + vaddr.level1();
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AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte);
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if (!level1.valid()) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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Addr level2_pte = level1.paddr() + vaddr.level2();
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AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte);
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if (!level2.valid()) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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Addr level3_pte = level2.paddr() + vaddr.level3();
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AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte);
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if (!level3.valid()) {
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DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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return level3;
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}
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Addr
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vtophys(PhysicalMemory *xc, Addr vaddr)
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{
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Addr paddr = 0;
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if (AlphaISA::IsUSeg(vaddr))
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (AlphaISA::IsK0Seg(vaddr))
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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vtophys(ExecContext *xc, Addr addr)
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{
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AlphaISA::VAddr vaddr = addr;
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Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
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paddr = vaddr & ~ULL(1);
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} else {
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if (AlphaISA::IsK0Seg(vaddr)) {
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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} else if (!ptbr) {
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paddr = vaddr;
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} else {
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AlphaISA::PageTableEntry pte =
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kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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if (pte.valid())
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paddr = pte.paddr() | vaddr.offset();
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}
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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uint8_t *
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ptomem(ExecContext *xc, Addr paddr, size_t len)
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{
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return xc->physmem->dma_addr(paddr, len);
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}
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uint8_t *
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vtomem(ExecContext *xc, Addr vaddr, size_t len)
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{
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Addr paddr = vtophys(xc, vaddr);
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return xc->physmem->dma_addr(paddr, len);
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}
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void
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CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *dst = (char *)dest;
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int len;
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paddr = vtophys(xc, src);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, len);
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if (len == cplen)
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return;
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cplen -= len;
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dst += len;
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src += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, cplen);
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}
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}
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void
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CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *src = (char *)source;
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int len;
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paddr = vtophys(xc, dest);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dmaaddr, src, len);
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if (len == cplen)
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return;
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cplen -= len;
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src += len;
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dest += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dmaaddr, src, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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dest += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dmaaddr, src, cplen);
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}
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}
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void
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CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
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{
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Addr paddr;
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char *dmaaddr;
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int len;
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paddr = vtophys(xc, vaddr);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)maxlen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, len);
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if (term)
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len = term - dmaaddr + 1;
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memcpy(dst, dmaaddr, len);
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if (term || len == maxlen)
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return;
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maxlen -= len;
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dst += len;
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vaddr += len;
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while (maxlen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
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len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes;
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memcpy(dst, dmaaddr, len);
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if (term)
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return;
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maxlen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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vaddr += AlphaISA::PageBytes;
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}
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if (maxlen > 0) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, maxlen);
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len = term ? (term - dmaaddr + 1) : maxlen;
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memcpy(dst, dmaaddr, len);
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maxlen -= len;
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}
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if (maxlen == 0)
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dst[maxlen] = '\0';
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}
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