2864 lines
326 KiB
Text
2864 lines
326 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000108 # Number of seconds simulated
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sim_ticks 107944000 # Number of ticks simulated
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final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 128828 # Simulator instruction rate (inst/s)
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host_op_rate 128828 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 13989470 # Simulator tick rate (ticks/s)
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host_mem_usage 239356 # Number of bytes of host memory used
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host_seconds 7.72 # Real time elapsed on the host
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sim_insts 994048 # Number of instructions simulated
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sim_ops 994048 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 42816 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 669 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 670 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 115 # Per bank write bursts
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system.physmem.perBankRdBursts::1 42 # Per bank write bursts
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system.physmem.perBankRdBursts::2 27 # Per bank write bursts
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system.physmem.perBankRdBursts::3 60 # Per bank write bursts
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system.physmem.perBankRdBursts::4 66 # Per bank write bursts
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system.physmem.perBankRdBursts::5 28 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24 # Per bank write bursts
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system.physmem.perBankRdBursts::8 7 # Per bank write bursts
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system.physmem.perBankRdBursts::9 29 # Per bank write bursts
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system.physmem.perBankRdBursts::10 23 # Per bank write bursts
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system.physmem.perBankRdBursts::11 14 # Per bank write bursts
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system.physmem.perBankRdBursts::12 65 # Per bank write bursts
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system.physmem.perBankRdBursts::13 38 # Per bank write bursts
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system.physmem.perBankRdBursts::14 17 # Per bank write bursts
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system.physmem.perBankRdBursts::15 97 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 107916000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 670 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
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system.physmem.totQLat 6539750 # Total ticks spent queuing
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system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 3.10 # Data bus utilization in percentage
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system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 511 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 161068.66 # Average gap between requests
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system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ)
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system.physmem_0.averagePower 750.559832 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states
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system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 728.745214 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu0.branchPred.lookups 81450 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.workload.num_syscalls 89 # Number of system calls
|
|
system.cpu0.numCycles 215889 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing
|
|
system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename
|
|
system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups
|
|
system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 13187 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued
|
|
system.cpu0.iq.rate 1.792574 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 404550 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 72936 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 76534 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 74459 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 1.787706 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 228400 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 450384 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 219907 # Number of memory references committed
|
|
system.cpu0.commit.loads 146267 # Number of loads committed
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 75527 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 303686 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 649458 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 931043 # The number of ROB writes
|
|
system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.committedInsts 378041 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 690199 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 311415 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 2 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits
|
|
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
|
|
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 148458 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses
|
|
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
|
|
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1053 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 323 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 6428 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 797 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 52261 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu1.numCycles 162232 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename
|
|
system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups
|
|
system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 13593 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued
|
|
system.cpu1.iq.rate 1.386958 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 243255 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 36391 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 45914 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 34905 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 1.380418 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 126652 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 251602 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 106422 # Number of memory references committed
|
|
system.cpu1.commit.loads 72360 # Number of loads committed
|
|
system.cpu1.commit.membars 4751 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 44778 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 173320 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 417798 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 534614 # The number of ROB writes
|
|
system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 211284 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 386957 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 181537 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 77097 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 619 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 385 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 21045 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 578 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.branchPred.lookups 51309 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu2.numCycles 161860 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename
|
|
system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups
|
|
system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 13773 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued
|
|
system.cpu2.iq.rate 1.362270 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 239427 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 36005 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 45327 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 33515 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.355350 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 123331 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 246921 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 103190 # Number of memory references committed
|
|
system.cpu2.commit.loads 70499 # Number of loads committed
|
|
system.cpu2.commit.membars 5644 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 44296 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 169605 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
|
|
system.cpu2.rob.rob_reads 416888 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 525783 # The number of ROB writes
|
|
system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 206194 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 376797 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 176595 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 75268 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 573 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 384 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 22324 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 560 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.branchPred.lookups 49957 # Number of BP lookups
|
|
system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted
|
|
system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect
|
|
system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups
|
|
system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits
|
|
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage
|
|
system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
|
|
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu3.numCycles 161075 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename
|
|
system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full
|
|
system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
|
|
system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups
|
|
system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 13428 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued
|
|
system.cpu3.iq.rate 1.322999 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 231462 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 34658 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 44015 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 31810 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 1.315989 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 118601 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value
|
|
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back
|
|
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 238347 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 98515 # Number of memory references committed
|
|
system.cpu3.commit.loads 67516 # Number of loads committed
|
|
system.cpu3.commit.membars 6034 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 42994 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 163632 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction
|
|
system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached
|
|
system.cpu3.rob.rob_reads 408052 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 507784 # The number of ROB writes
|
|
system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 198529 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 362535 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 170128 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 72250 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 577 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 387 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 23109 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 560 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1669 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 20118 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 20118 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1669 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 251 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 414 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 481 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 491 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
|
system.l2c.overall_hits::total 1669 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 551 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 682 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 364 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 169 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 83 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 7 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
|
system.l2c.overall_misses::total 682 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.290089 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.167002 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.026316 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.290089 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76350.274725 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 80056.666667 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77060.240964 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79035.714286 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.769231 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 96750 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 70785.714286 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.data 82500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 77206.442831 # average ReadReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 86500 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86576.923077 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 85032.442748 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 78709.677419 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 78709.677419 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 7 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.inst 5 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 7 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 7 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles
|
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system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles
|
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system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles
|
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system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles
|
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system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles
|
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system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles
|
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|
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system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles
|
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system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles
|
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system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 539 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 538 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 171 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 240 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 986 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 986 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
|
|
system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1012 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|