5200e04e92
Although the cache models support wider accesses, the ISA descriptions assume that (for the most part) memory operands are integer types, which makes it difficult to define instructions that do memory accesses larger than 64 bits. This patch adds some generic support for memory operands that are arrays of uint64_t, and specifically a 'u2qw' operand type for x86 that is an array of 2 uint64_ts (128 bits). This support is unused at this point, but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE memory accesses will also be rewritten to use this support. Support for 128-bit accesses could also have been added using the gcc __int128_t extension, which would have been less disruptive. However, although clang also supports __int128_t, it's still non-standard. Also, more importantly, this approach creates a path to defining 256- and 512-byte operands as well, which will be useful for eventual AVX support.
556 lines
19 KiB
Plaintext
556 lines
19 KiB
Plaintext
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2008 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// LdStOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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// LEA template
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def template MicroLeaExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLeaDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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%(BasicExecDeclare)s
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};
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}};
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// Load templates
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def template MicroLoadExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
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if (fault == NoFault) {
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%(code)s;
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} else if (memFlags & Request::PREFETCH) {
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// For prefetches, ignore any faults/exceptions.
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return NoFault;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
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return fault;
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}
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}};
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def template MicroLoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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getMem(pkt, Mem, dataSize, traceData);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Store templates
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def template MicroStoreExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
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memFlags, NULL);
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template MicroStoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
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memFlags, NULL);
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}
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return fault;
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}
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}};
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def template MicroStoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const
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{
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%(op_decl)s;
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%(op_rd)s;
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%(complete_code)s;
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%(op_wb)s;
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return NoFault;
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}
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}};
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// Common templates
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//This delcares the initiateAcc function in memory operations
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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//This declares the completeAcc function in memory operations
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template MicroLdStOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template MicroLdStOpConstructor {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
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_scale, _index, _base,
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_disp, _segment, _data,
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_dataSize, _addressSize, _memFlags, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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let {{
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class LdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.instFlags = ""
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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def getAllocator(self, microFlags):
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(scale)s, %(index)s, %(base)s,
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%(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.instFlags = ""
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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def getAllocator(self, microFlags):
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allocString = '''
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(%(dataSize)s >= 4) ?
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(StaticInstPtr)(new %(class_name)sBig(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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calculateEA = '''
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EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
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'''
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def defineMicroLoadOp(mnemonic, code, bigCode='',
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mem_flags="0", big=True):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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Name = mnemonic
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name = mnemonic.lower()
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# Build up the all register version of this micro op
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iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
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{"code": code, "ea_code": calculateEA})]
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if big:
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iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
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{"code": bigCode, "ea_code": calculateEA})]
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for iop in iops:
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header_output += MicroLdStOpDeclare.subst(iop)
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decoder_output += MicroLdStOpConstructor.subst(iop)
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exec_output += MicroLoadExecute.subst(iop)
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exec_output += MicroLoadInitiateAcc.subst(iop)
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exec_output += MicroLoadCompleteAcc.subst(iop)
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base = LdStOp
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if big:
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base = BigLdStOp
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class LoadOp(base):
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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atCPL0=False, prefetch=False, nonSpec=False):
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super(LoadOp, self).__init__(data, segment, addr,
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disp, dataSize, addressSize, mem_flags,
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atCPL0, prefetch, nonSpec)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = LoadOp
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defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);')
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defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift)')
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defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift) | Request::LOCKED_RMW')
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defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
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defineMicroLoadOp('Ldfp87', code='''
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switch (dataSize)
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{
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case 4:
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FpData_df = *(float *)&Mem;
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break;
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case 8:
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FpData_df = *(double *)&Mem;
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break;
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default:
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panic("Unhandled data size in LdFp87.\\n");
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}
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''', big = False)
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# Load integer from memory into x87 top-of-stack register.
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# Used to implement fild instruction.
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defineMicroLoadOp('Ldifp87', code='''
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switch (dataSize)
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{
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case 2:
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FpData_df = (int64_t)sext<16>(Mem);
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break;
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case 4:
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FpData_df = (int64_t)sext<32>(Mem);
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break;
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case 8:
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FpData_df = (int64_t)Mem;
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break;
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default:
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panic("Unhandled data size in LdIFp87.\\n");
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}
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''', big = False)
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def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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Name = mnemonic
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name = mnemonic.lower()
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# Build up the all register version of this micro op
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iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
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{"code": code,
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"complete_code": completeCode,
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"ea_code": calculateEA})
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header_output += MicroLdStOpDeclare.subst(iop)
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decoder_output += MicroLdStOpConstructor.subst(iop)
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exec_output += MicroStoreExecute.subst(iop)
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exec_output += MicroStoreInitiateAcc.subst(iop)
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exec_output += MicroStoreCompleteAcc.subst(iop)
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class StoreOp(LdStOp):
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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atCPL0=False, nonSpec=False):
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super(StoreOp, self).__init__(data, segment, addr, disp,
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dataSize, addressSize, mem_flags, atCPL0, False,
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nonSpec)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = StoreOp
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defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
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defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
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mem_flags="Request::LOCKED_RMW")
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defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
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defineMicroStoreOp('Stfp87', code='''
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switch (dataSize)
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{
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case 4: {
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float single(FpData_df);
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Mem = *(uint32_t *)&single;
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} break;
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case 8:
|
|
Mem = *(uint64_t *)&FpData_df;
|
|
break;
|
|
default:
|
|
panic("Unhandled data size in StFp87.\\n");
|
|
}
|
|
''')
|
|
|
|
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
|
|
|
|
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
|
|
{"code": "Data = merge(Data, EA, dataSize);",
|
|
"ea_code": '''
|
|
EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
|
|
'''})
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
class LeaOp(LdStOp):
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
|
super(LeaOp, self).__init__(data, segment, addr, disp,
|
|
dataSize, addressSize, "0", False, False, False)
|
|
self.className = "Lea"
|
|
self.mnemonic = "lea"
|
|
|
|
microopClasses["lea"] = LeaOp
|
|
|
|
|
|
iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
|
|
{"code": "xc->demapPage(EA, 0);",
|
|
"ea_code": calculateEA})
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
class TiaOp(LdStOp):
|
|
def __init__(self, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize"):
|
|
super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
|
addr, disp, dataSize, addressSize, "0", False, False,
|
|
False)
|
|
self.className = "Tia"
|
|
self.mnemonic = "tia"
|
|
|
|
microopClasses["tia"] = TiaOp
|
|
|
|
class CdaOp(LdStOp):
|
|
def __init__(self, segment, addr, disp = 0,
|
|
dataSize="env.dataSize",
|
|
addressSize="env.addressSize", atCPL0=False):
|
|
super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
|
addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
|
|
atCPL0, False, False)
|
|
self.className = "Cda"
|
|
self.mnemonic = "cda"
|
|
|
|
microopClasses["cda"] = CdaOp
|
|
}};
|
|
|