149 lines
4.9 KiB
C++
149 lines
4.9 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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*/
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/**
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* @file
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* Describes a strided prefetcher based on template policies.
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*/
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#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
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#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
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#include "base/misc.hh" // fatal, panic, and warn
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#include "mem/cache/prefetch/prefetcher.hh"
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/**
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* A template-policy based cache. The behavior of the cache can be altered by
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* supplying different template policies. TagStore handles all tag and data
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* storage @sa TagStore. Buffering handles all misses and writes/writebacks
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* @sa MissQueue. Coherence handles all coherence policy details @sa
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* UniCoherence, SimpleMultiCoherence.
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*/
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template <class TagStore, class Buffering>
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class StridePrefetcher : public Prefetcher<TagStore, Buffering>
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{
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protected:
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Buffering* mq;
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TagStore* tags;
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class strideEntry
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{
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public:
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Addr IAddr;
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Addr MAddr;
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int stride;
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int64_t confidence;
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/* bool operator < (strideEntry a,strideEntry b)
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{
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if (a.confidence == b.confidence) {
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return true; //??????
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}
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else return a.confidence < b.confidence;
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}*/
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};
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Addr* lastMissAddr[64/*MAX_CPUS*/];
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std::list<strideEntry*> table[64/*MAX_CPUS*/];
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Tick latency;
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int degree;
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bool useCPUId;
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public:
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StridePrefetcher(int size, bool pageStop, bool serialSquash,
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bool cacheCheckPush, bool onlyData,
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Tick latency, int degree, bool useCPUId)
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:Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
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cacheCheckPush, onlyData),
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latency(latency), degree(degree), useCPUId(useCPUId)
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{
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}
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~StridePrefetcher() {}
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void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
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std::list<Tick> &delays)
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{
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// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
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int cpuID = pkt->req->getCpuNum();
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if (!useCPUId) cpuID = 0;
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/* Scan Table for IAddr Match */
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/* std::list<strideEntry*>::iterator iter;
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for (iter=table[cpuID].begin();
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iter !=table[cpuID].end();
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iter++) {
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if ((*iter)->IAddr == pkt->pc) break;
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}
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if (iter != table[cpuID].end()) {
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//Hit in table
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int newStride = blkAddr - (*iter)->MAddr;
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if (newStride == (*iter)->stride) {
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(*iter)->confidence++;
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}
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else {
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(*iter)->stride = newStride;
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(*iter)->confidence--;
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}
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(*iter)->MAddr = blkAddr;
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for (int d=1; d <= degree; d++) {
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Addr newAddr = blkAddr + d * newStride;
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if (this->pageStop &&
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(blkAddr & ~(TheISA::VMPageSize - 1)) !=
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(newAddr & ~(TheISA::VMPageSize - 1)))
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{
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//Spanned the page, so now stop
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this->pfSpanPage += degree - d + 1;
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return;
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}
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else
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{
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addresses.push_back(newAddr);
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delays.push_back(latency);
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}
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}
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}
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else {
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//Miss in table
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//Find lowest confidence and replace
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}
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*/ }
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};
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#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
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