c39aea440c
and resulting recursive import trickiness. --HG-- extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
29 lines
1.2 KiB
Python
29 lines
1.2 KiB
Python
from m5.params import *
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from m5.proxy import *
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from MemObject import *
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class PhysicalMemory(MemObject):
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type = 'PhysicalMemory'
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port = Port("the access port")
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range = Param.AddrRange(AddrRange('128MB'), "Device Address")
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file = Param.String('', "memory mapped file")
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latency = Param.Latency(Parent.clock, "latency of an access")
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class DRAMMemory(PhysicalMemory):
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type = 'DRAMMemory'
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# Many of these should be observed from the configuration
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cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
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mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
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mem_actpolicy = Param.String("open", "Open/Close policy")
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memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
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bus_width = Param.Int(16, "")
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act_lat = Param.Int(2, "RAS to CAS delay")
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cas_lat = Param.Int(1, "CAS delay")
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war_lat = Param.Int(2, "write after read delay")
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pre_lat = Param.Int(2, "precharge delay")
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dpl_lat = Param.Int(2, "data in to precharge delay")
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trc_lat = Param.Int(6, "row cycle delay")
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num_banks = Param.Int(4, "Number of Banks")
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num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
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